[PATCH 02/17] drm/msm: a6xx: Refactor a6xx_sptprac_enable()

[Akhil P Oommen]

A minor refactor to combine the subroutines for legacy a6xx GMUs under
a single check. This helps to avoid an unnecessary check and return
early from the subroutine for majority of a6xx gpus.

Signed-off-by: Akhil P Oommen <akhi...@oss.qualcomm.com>
---
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c 
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 
38c0f8ef85c3d260864541d83abe43e49c772c52..41129692d127b70e9293b82bea5ccb6b911b0bfb
 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -403,7 +403,10 @@ int a6xx_sptprac_enable(struct a6xx_gmu *gmu)
        int ret;
        u32 val;
 
-       if (!gmu->legacy)
+       WARN_ON(!gmu->legacy);
+
+       /* Nothing to do if GMU does the power management */
+       if (gmu->idle_level > GMU_IDLE_STATE_ACTIVE)
                return 0;
 
        gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000);
@@ -925,10 +928,7 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, 
unsigned int state)
                ret = a6xx_gmu_gfx_rail_on(gmu);
                if (ret)
                        return ret;
-       }
 
-       /* Enable SPTP_PC if the CPU is responsible for it */
-       if (gmu->idle_level < GMU_IDLE_STATE_SPTP) {
                ret = a6xx_sptprac_enable(gmu);
                if (ret)
                        return ret;

-- 
2.50.1