On 7/23/2025 3:31 PM, Konrad Dybcio wrote: > On 7/20/25 2:16 PM, Akhil P Oommen wrote: >> A7XX_GEN2 generation has additional TCS slots. Poll the respective >> DRV status registers before pm suspend. >> >> Signed-off-by: Akhil P Oommen <akhi...@oss.qualcomm.com> >> --- >> drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 16 ++++++++++++++++ >> 1 file changed, 16 insertions(+) >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> index >> 790ef2f94a0b0cd40433d7edb6a89e4f04408bf5..3bebb6dd7059782ceca29f2efd2acee24d3fc930 >> 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c >> @@ -987,6 +987,22 @@ static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu) >> val, (val & 1), 100, 10000); >> gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS + seqmem_off, >> val, (val & 1), 100, 1000);
1000us here is a typo and I copied the same mistake below. I will update all of these timeout values to a common 10000us in the next revision. >> + >> + if (!adreno_is_a740_family(adreno_gpu)) >> + return; >> + >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS4_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 10000); >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS5_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 10000); >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS6_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 10000); >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS7_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 1000); >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS8_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 10000); >> + gmu_poll_timeout_rscc(gmu, REG_A7XX_RSCC_TCS9_DRV0_STATUS + seqmem_off, >> + val, (val & 1), 100, 1000); > > FWIW there are places downstream where it polls for 1 ms > (gen7_gmu_pwrctrl_suspend) / 2 ms (gen7_gmu_power_off) ms (as opposed > to 1 or 10 ms here), but the timeouts are all the same across registers > (unlike TCS3 and TCS9 above) > > Ultimately it's a timeout, so a value too big shouldn't matter, but > let's make sure the other threshold is ok They are fine. We can try to reduce the timeout 2ms in a separate patch outside of this series. -Akhil. > > Konrad
