On 9/3/25 4:00 PM, Dmitry Baryshkov wrote:
> On Wed, Sep 03, 2025 at 03:36:34PM +0200, Konrad Dybcio wrote:
>> On 9/3/25 2:39 PM, Dmitry Baryshkov wrote:
>>> On Wed, Sep 03, 2025 at 02:26:30PM +0200, Konrad Dybcio wrote:
>>>> On 8/21/25 8:55 PM, Akhil P Oommen wrote:
>>>>> From: Puranam V G Tejaswi <quic_pvgte...@quicinc.com>
>>>>>
>>>>> Add gpu and gmu nodes for sa8775p chipset. As of now all
>>>>> SKUs have the same GPU fmax, so there is no requirement of
>>>>> speed bin support.
>>>>>
>>>>> Signed-off-by: Puranam V G Tejaswi <quic_pvgte...@quicinc.com>
>>>>> Signed-off-by: Akhil P Oommen <akhi...@oss.qualcomm.com>
>>>>> Reviewed-by: Dmitry Baryshkov <dmitry.barysh...@linaro.org>
>>>>> ---
>>>>> arch/arm64/boot/dts/qcom/lemans.dtsi | 116
>>>>> +++++++++++++++++++++++++++++++++++
>>>>> 1 file changed, 116 insertions(+)
>>>>>
>>>>> diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi
>>>>> b/arch/arm64/boot/dts/qcom/lemans.dtsi
>>>>> index
>>>>> 8ceb59742a9fc6562b2c38731ddabe3a549f7f35..8eac8d4719db9230105ad93ac22287850b6b007c
>>>>> 100644
>>>>> --- a/arch/arm64/boot/dts/qcom/lemans.dtsi
>>>>> +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi
>>>>> @@ -1097,6 +1097,18 @@ ipcc: mailbox@408000 {
>>>>> #mbox-cells = <2>;
>>>>> };
>>>>>
>>>>> + qfprom: efuse@784000 {
>>>>> + compatible = "qcom,sa8775p-qfprom", "qcom,qfprom";
>>>>> + reg = <0x0 0x00784000 0x0 0x2410>;
>>>>
>>>> len = 0x3000
>>>>
>>>> [...]
>>>>
>>>>> + gmu: gmu@3d6a000 {
>>>>> + compatible = "qcom,adreno-gmu-663.0", "qcom,adreno-gmu";
>>>>> + reg = <0x0 0x03d6a000 0x0 0x34000>,
>>>>
>>>> This bleeds into GPU_CC, len should be 0x26000
>>>
>>> gpucc is in the middle of GMU, see other platforms.
>>
>> This is not the case here
>
> Why? I think GPU CC is a part of the GMU by design: GMU accesses GPU CC
> registers directly from the firmware.
Correct, however this is only a similarly sounding argument - the DT
describes the hardware from the main Arm cluster POV. The GMU Cortex-M
core has its own address map etc.
Konrad
