Krzysztof, all,
On 9/9/25 3:56 AM, Krzysztof Kozlowski wrote:
On 05/09/2025 13:33, Linus Walleij wrote:
On Fri, Sep 5, 2025 at 12:02 PM Dmitry Torokhov
<dmitry.torok...@gmail.com> wrote:
On Thu, Aug 21, 2025 at 01:56:24PM +0200, Linus Walleij wrote:
Hi Ariel,
thanks for your patch!
On Wed, Aug 20, 2025 at 7:17 PM Ariel D'Alessandro
<ariel.dalessan...@collabora.com> wrote:
+ ce-gpios:
+ description: GPIO connected to the CE (chip enable) pin of the chip
+ maxItems: 1
Mention that this should always have the flag GPIO_ACTIVE_HIGH
as this is required by the hardware.
Unfortunately we have no YAML syntax for enforcing flags :/
Theoretically there can be an inverter on the line, so from the AP point
of view the line is active low while from the peripheral POV the pin is
active high...
Yes, I think someone even proposed adding inverters to the
device tree and was nixed.
It's not about DT, it's about board design - you can (almost?) always
invert the logical signal, so this should match what hardware requires
plus any inverter on the board.
It's a matter of phrasing I would say:
"Mention that this should nominally have the flag GPIO_ACTIVE_HIGH
No, please do not, it is wrong. If hardware requires active high, then
just say this is active high. But the actual GPIO flag depends on the
board design if signal is inverted.
After the discussion from this thread, will mark it a "active high" in
the property description for v2.
Thanks,
--
Ariel D'Alessandro
Software Engineer
Collabora Ltd.
Platinum Building, St John's Innovation Park, Cambridge CB4 0DS, UK
Registered in England & Wales, no. 5513718
