On the MediaTek MT8196 SoC, the GPU has its power and frequency dynamically controlled by an embedded special-purpose MCU. This MCU is in charge of powering up the GPU silicon. It also provides us with a list of available OPPs at runtime, and is fully in control of all the regulator and clock fiddling it takes to reach a certain level of performance. It's also in charge of enforcing limits on power draw or temperature.
Add a binding for this device in the devfreq subdirectory, where it seems to fit in best considering its tasks. Signed-off-by: Nicolas Frattaroli <nicolas.frattar...@collabora.com> --- .../bindings/devfreq/mediatek,mt8196-gpufreq.yaml | 113 +++++++++++++++++++++ 1 file changed, 113 insertions(+) diff --git a/Documentation/devicetree/bindings/devfreq/mediatek,mt8196-gpufreq.yaml b/Documentation/devicetree/bindings/devfreq/mediatek,mt8196-gpufreq.yaml new file mode 100644 index 0000000000000000000000000000000000000000..9d9efd4e70f1ef7ae446c833c15144beb9641b16 --- /dev/null +++ b/Documentation/devicetree/bindings/devfreq/mediatek,mt8196-gpufreq.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/devfreq/mediatek,mt8196-gpufreq.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MFlexGraphics Performance Controller + +maintainers: + - Nicolas Frattaroli <nicolas.frattar...@collabora.com> + +description: | + A special-purpose embedded MCU to control power and frequency of GPU devices + using MediaTek Flexible Graphics integration hardware. + +properties: + $nodename: + pattern: '^performance-controller@[a-f0-9]+$' + + compatible: + enum: + - mediatek,mt8196-gpufreq + + reg: + items: + - description: GPR memory area + - description: RPC memory area + - description: SoC variant ID register + + reg-names: + items: + - const: gpr + - const: rpc + - const: hw_revision + + clocks: + items: + - description: main clock of the embedded controller (EB) + - description: core PLL + - description: stack 0 PLL + - description: stack 1 PLL + + clock-names: + items: + - const: eb + - const: mfgpll + - const: mfgpll_sc0 + - const: mfgpll_sc1 + + mboxes: + items: + - description: FastDVFS events + - description: frequency control + - description: sleep control + - description: timer control + - description: frequency hopping control + - description: hardware voter control + - description: FastDVFS control + + mbox-names: + items: + - const: fast-dvfs-event + - const: gpufreq + - const: sleep + - const: timer + - const: fhctl + - const: ccf + - const: fast-dvfs + + shmem: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the shared memory region of the GPUEB MCU + + "#performance-domain-cells": + const: 0 + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - mboxes + - mbox-names + - shmem + - "#performance-domain-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mediatek,mt8196-clock.h> + + gpufreq: performance-controller@4b09fd00 { + compatible = "mediatek,mt8196-gpufreq"; + reg = <0x4b09fd00 0x80>, + <0x4b800000 0x1000>, + <0x4b860128 0x4>; + reg-names = "gpr", "rpc", "hw_revision"; + clocks = <&topckgen CLK_TOP_MFG_EB>, + <&mfgpll CLK_MFG_AO_MFGPLL>, + <&mfgpll_sc0 CLK_MFGSC0_AO_MFGPLL_SC0>, + <&mfgpll_sc1 CLK_MFGSC1_AO_MFGPLL_SC1>; + clock-names = "eb", "mfgpll", "mfgpll_sc0", + "mfgpll_sc1"; + mboxes = <&gpueb_mbox 0>, <&gpueb_mbox 1>, <&gpueb_mbox 2>, + <&gpueb_mbox 3>, <&gpueb_mbox 4>, <&gpueb_mbox 5>, + <&gpueb_mbox 7>; + mbox-names = "fast-dvfs-event", "gpufreq", "sleep", "timer", "fhctl", + "ccf", "fast-dvfs"; + shmem = <&gpufreq_shmem>; + #performance-domain-cells = <0>; + }; -- 2.51.0
