On Mon, Sep 15, 2025 at 07:29:08PM +0800, Xiangxu Yin wrote:
>
> On 9/12/2025 6:12 PM, Dmitry Baryshkov wrote:
> > On Thu, Sep 11, 2025 at 10:55:04PM +0800, Xiangxu Yin wrote:
> >> Introduce DisplayPort PHY configuration routines for QCS615, including
> >> aux channel setup, lane control, voltage swing tuning, clock config and
> >> calibration. These callbacks are registered via qmp_phy_cfg to enable DP
> >> mode on USB/DP switchable Type-C PHYs.
> >>
> >> Add register define for QMP_DP_PHY_V2 series.
> >>
> >> Signed-off-by: Xiangxu Yin <xiangxu....@oss.qualcomm.com>
> >> ---
> >> drivers/phy/qualcomm/phy-qcom-qmp-dp-phy-v2.h | 21 +++
> >> drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 251
> >> ++++++++++++++++++++++++++
> >> 2 files changed, 272 insertions(+)
> >>
> >> +static int qcs615_qmp_calibrate_dp_phy(struct qmp_usbc *qmp)
> >> +{
> >> + static const u8 cfg1_settings[] = {0x13, 0x23, 0x1d};
> > Are these the actual values or is it a C&P from the combo PHY?
>
>
> These configurations are the same as those in combo, and I have compared
> that they match the downstream sm6150 project configuration.
Let's keep them as is, thanks for the confirmation that you checked it
against the vendor kernel.
>
> From hardware programing guide, only defined AUX sequance withÂ
> DP_PHY_PD_CTL set to 0x3d and DP_PHY_AUX_CFG1 set to 0x13.
>
> Shall I update table to {0x13} only?
>
>
> >> + u8 val;
> >> +
> >> + qmp->dp_aux_cfg++;
> >> + qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
> >> + val = cfg1_settings[qmp->dp_aux_cfg];
> >> +
> >> + writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
> >> +
> >> + return 0;
> >> +}
> >> +
> >> static int qmp_usbc_usb_power_on(struct phy *phy)
> >> {
> >> struct qmp_usbc *qmp = phy_get_drvdata(phy);
> >>
> >> --
> >> 2.34.1
> >>
--
With best wishes
Dmitry
