On 9/30/25 7:48 AM, Akhil P Oommen wrote: > GMU registers are always at a fixed offset from the GPU base address, > a consistency maintained at least within a given architecture generation. > In A8x family, the base address of the GMU has changed, but the offsets > of the gmu registers remain largely the same. To enable reuse of the gmu > code for A8x chipsets, update the gmu register offsets to be relative > to the GPU's base address instead of GMU's. > > Signed-off-by: Akhil P Oommen <[email protected]> > --- > drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 44 +++- > drivers/gpu/drm/msm/adreno/a6xx_gmu.h | 20 +- > drivers/gpu/drm/msm/registers/adreno/a6xx_gmu.xml | 248 > +++++++++++----------- > 3 files changed, 172 insertions(+), 140 deletions(-) > > diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > index > fc717c9474ca5bdd386a8e4e19f43abce10ce591..72d64eb10ca931ee90c91f7e004771cf6d7997a4 > 100644 > --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c > @@ -585,14 +585,14 @@ static inline void pdc_write(void __iomem *ptr, u32 > offset, u32 value) > } > > static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev, > - const char *name); > + const char *name, resource_size_t *start);
Maybe you can keep this offset variant and switch to a simple devm_platform_get_and_ioremap_resource() for others (also letting us get rid of a number of iounmap() calls) [...] > + /* The 'offset' is based on GPU's start address. Adjust it */ That's what an offset is, no? ;) I think we can drop this comment or move it above the #define Konrad
