On 10/14/2025 6:18 PM, Dmitry Baryshkov wrote:
> On Tue, Oct 14, 2025 at 05:42:11PM +0800, Xiangxu Yin via B4 Relay wrote:
>> From: Xiangxu Yin <[email protected]>
>>
>> Introduce DisplayPort controller node and associated QMP USB3-DP PHY
>> for SM6150 SoC. Update clock and endpoint connections to enable DP
>> integration.
>>
>> Signed-off-by: Xiangxu Yin <[email protected]>
>> ---
>> arch/arm64/boot/dts/qcom/sm6150.dtsi | 110
>> ++++++++++++++++++++++++++++++++++-
>> 1 file changed, 108 insertions(+), 2 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm6150.dtsi
>> b/arch/arm64/boot/dts/qcom/sm6150.dtsi
>> index
>> 6128d8c48f9c0807ac488ddac3b2377678e8f8c3..cdf53d74c778c652080b0288278353e20c317379
>> 100644
>> --- a/arch/arm64/boot/dts/qcom/sm6150.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm6150.dtsi
>> @@ -17,6 +17,7 @@
>> #include <dt-bindings/power/qcom-rpmpd.h>
>> #include <dt-bindings/power/qcom,rpmhpd.h>
>> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>> +#include <dt-bindings/phy/phy-qcom-qmp.h>
>>
>> / {
>> interrupt-parent = <&intc>;
>> @@ -3717,6 +3718,7 @@ port@0 {
>> reg = <0>;
>>
>> dpu_intf0_out: endpoint {
>> + remote-endpoint =
>> <&mdss_dp0_in>;
>> };
>> };
>>
>> @@ -3749,6 +3751,84 @@ opp-307200000 {
>> };
>> };
>>
>> + mdss_dp0: displayport-controller@ae90000 {
>> + compatible = "qcom,sm6150-dp",
>> "qcom,sm8150-dp", "qcom,sm8350-dp";
>> +
>> + reg = <0x0 0x0ae90000 0x0 0x200>,
>> + <0x0 0x0ae90200 0x0 0x200>,
>> + <0x0 0x0ae90400 0x0 0x600>,
>> + <0x0 0x0ae90a00 0x0 0x600>,
>> + <0x0 0x0ae91000 0x0 0x600>;
>> +
>> + interrupt-parent = <&mdss>;
>> + interrupts = <12>;
>> +
>> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
>> + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
>> + <&dispcc
>> DISP_CC_MDSS_DP_LINK_INTF_CLK>,
>> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>,
>> + <&dispcc DISP_CC_MDSS_DP_PIXEL1_CLK>;
>> + clock-names = "core_iface",
>> + "core_aux",
>> + "ctrl_link",
>> + "ctrl_link_iface",
>> + "stream_pixel",
>> + "stream_1_pixel";
>> +
>> + assigned-clocks = <&dispcc
>> DISP_CC_MDSS_DP_LINK_CLK_SRC>,
>> + <&dispcc
>> DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
>> + assigned-clock-parents = <&usb_qmpphy_2
>> QMP_USB43DP_DP_LINK_CLK>,
>> + <&usb_qmpphy_2
>> QMP_USB43DP_DP_VCO_DIV_CLK>;
> Missing PIXEL1_CLK_SRC assignment
Ok, will update in next patch.
>> +
>> + phys = <&usb_qmpphy_2 QMP_USB43DP_DP_PHY>;
>> + phy-names = "dp";
>> +
>> + operating-points-v2 = <&dp_opp_table>;
>> + power-domains = <&rpmhpd RPMHPD_CX>;
>> +
>> + #sound-dai-cells = <0>;
>> +
>> + status = "disabled";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + mdss_dp0_in: endpoint {
>> + remote-endpoint =
>> <&dpu_intf0_out>;
>> + };
>> + };
>> +
>> + port@1 {
>> + reg = <1>;
>> + mdss_dp0_out: endpoint {
> I thought that we need a data-lanes property somewhere here.
Ok, will update.
>> + };
>> + };
>> + };
>> +
