Document NXP i.MX95 pixel interleaver bridge support. Signed-off-by: Marek Vasut <[email protected]> --- Cc: Abel Vesa <[email protected]> Cc: Conor Dooley <[email protected]> Cc: Fabio Estevam <[email protected]> Cc: Krzysztof Kozlowski <[email protected]> Cc: Laurent Pinchart <[email protected]> Cc: Liu Ying <[email protected]> Cc: Lucas Stach <[email protected]> Cc: Peng Fan <[email protected]> Cc: Pengutronix Kernel Team <[email protected]> Cc: Rob Herring <[email protected]> Cc: Shawn Guo <[email protected]> Cc: Thomas Zimmermann <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] --- .../bridge/fsl,imx95-pixel-interleaver.yaml | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx95-pixel-interleaver.yaml
diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx95-pixel-interleaver.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx95-pixel-interleaver.yaml new file mode 100644 index 0000000000000..6a0647f060a02 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx95-pixel-interleaver.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/fsl,imx95-pixel-interleaver.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX95 Display Pixel Interleaver + +maintainers: + - Liu Ying <[email protected]> + - Marek Vasut <[email protected]> + +description: | + The Freescale i.MX95 Display Pixel Interleaver receives and processes + 2 input display streams from the display controller and routes those + to 3 pixel link output ports. The interleaver is capable of YUV444 to + YUV422 conversion and pixel interleaving. + +properties: + compatible: + const: fsl,imx95-pixel-interleaver + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + fsl,syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + A phandle which points to Control and Status Registers (CSR) module. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: The pixel link input port node from upstream video source. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: The pixel link output port node to downstream bridge. + + required: + - port@0 + - port@1 + +required: + - compatible + - fsl,syscon + - ports + +additionalProperties: false + +examples: + - | + bridge@4b0d0000 { + compatible = "fsl,imx95-pixel-interleaver"; + reg = <0x4b0d0000 0x50>; + clocks = <&scmi_clk 0>; + fsl,syscon = <&dispmix_csr>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pixel_interleaver_disp0_to_dpu_disp0: endpoint { + remote-endpoint = <&dpu_disp0_to_pixel_interleaver_disp0>; + }; + }; + + port@1 { + reg = <1>; + + pixel_interleaver_disp0_to_display_pixel_link0: endpoint { + remote-endpoint = <&display_pixel_link0_to_pixel_interleaver_disp0>; + }; + }; + }; + }; -- 2.51.0
