Before the MIPI DSI clock source can be configured, the target divide ratio needs to be known.
Signed-off-by: Chris Brandt <[email protected]> Reviewed-by: Biju Das <[email protected]> Tested-by: Biju Das <[email protected]> --- v1->v2: - Add spaces around '/' in comments - Add target argument in new API v2->v3: - Add missing period in comment (Hugo) - Changed '1' to 'PLL5_TARGET_DSI' (Hugo) - Added Reviewed-by and Tested-by (Biju) --- .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c index 3b52dfc0ea1e..c9c5510bdd3e 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -7,6 +7,7 @@ #include <linux/bitfield.h> #include <linux/clk.h> +#include <linux/clk/renesas.h> #include <linux/delay.h> #include <linux/dma-mapping.h> #include <linux/io.h> @@ -732,6 +733,24 @@ static int rzg2l_mipi_dsi_host_attach(struct mipi_dsi_host *host, drm_bridge_add(&dsi->bridge); + /* + * Report required division ratio setting for the MIPI clock dividers. + * Assume the default clock source is FOUTPOSTDIV (PLL/2) being fed to the DSI-PHY, but also + * the DSI-PHY must be 16x the MIPI-DSI HS clock. + * + * pllclk / 2 = vclk * DSI divider + * pllclk = vclk * DSI divider * 2 + * + * hsclk = (vclk * DSI divider * 2) / 16 + * + * vclk * bpp = hsclk * 8 * num_lanes + * vclk * bpp = ((vclk * DSI divider * 2) / 16) * 8 * num_lanes + * which simplifies to... + * DSI divider = bpp / num_lanes + */ + rzg2l_cpg_dsi_div_set_divider(mipi_dsi_pixel_format_to_bpp(dsi->format) / dsi->lanes, + PLL5_TARGET_DSI); + return 0; } -- 2.50.1
