RE: [PATCH v3 1/2] clk: renesas: rzg2l: Remove DSI clock rate restrictions

[Chris Brandt]

Hi Hugo,

On Thu, Oct 23, 2025 2:03 PM, Hugo Villeneuve wrote:

> If you do that, you can also probably put this if() on as single line to 
> improve readability:
>
>     if (foutvco_rate <= PLL5_FOUTVCO_MIN ||  foutvco_rate >= PLL5_FOUTVCO_MAX)

You're right!
With 3 characters left to spare on the line :)

Thanks,
Chris