On Thu, Oct 23, 2025 at 02:59:12PM +0300, Dmitry Baryshkov wrote: > On Thu, Oct 23, 2025 at 03:53:52PM +0800, yuanjie yang wrote: > > From: Yuanjie Yang <[email protected]> > > > > DPU version 13 introduces changes to the interrupt register > > layout. Update the driver to support these modifications for > > proper interrupt handling. > > So... Previous patch enabled support for the platform and it has been > using wrong registers for interrupts? I think that's broken.
I want to express DPU 13 has different INTF register address, so need to add new interrupt array to let DPU 13 interrupt work fine. Maybe I should optimize my commit msg. > > > > Signed-off-by: Yongxing Mou <[email protected]> > > Signed-off-by: Yuanjie Yang <[email protected]> > > --- > > .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 89 ++++++++++++++++++- > > 1 file changed, 88 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > > index 49bd77a755aa..8d265581f6ec 100644 > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c > > @@ -40,6 +40,15 @@ > > #define MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(intf) > > (MDP_INTF_REV_7xxx_TEAR_OFF(intf) + 0x004) > > #define MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(intf) > > (MDP_INTF_REV_7xxx_TEAR_OFF(intf) + 0x008) > > > > +#define MDP_INTF_REV_13xx_OFF(intf) (0x18D000 + > > 0x1000 * (intf)) > > Lowercase hex OK, will fix. > > +#define MDP_INTF_REV_13xx_INTR_EN(intf) > > (MDP_INTF_REV_13xx_OFF(intf) + 0x1c0) > > +#define MDP_INTF_REV_13xx_INTR_STATUS(intf) > > (MDP_INTF_REV_13xx_OFF(intf) + 0x1c4) > > +#define MDP_INTF_REV_13xx_INTR_CLEAR(intf) > > (MDP_INTF_REV_13xx_OFF(intf) + 0x1c8) > > +#define MDP_INTF_REV_13xx_TEAR_OFF(intf) (0x18D800 + 0x1000 * > > (intf)) > > +#define MDP_INTF_REV_13xx_INTR_TEAR_EN(intf) > > (MDP_INTF_REV_13xx_TEAR_OFF(intf) + 0x000) > > +#define MDP_INTF_REV_13xx_INTR_TEAR_STATUS(intf) > > (MDP_INTF_REV_13xx_TEAR_OFF(intf) + 0x004) > > +#define MDP_INTF_REV_13xx_INTR_TEAR_CLEAR(intf) > > (MDP_INTF_REV_13xx_TEAR_OFF(intf) + 0x008) > > + > > /** > > * struct dpu_intr_reg - array of DPU register sets > > * @clr_off: offset to CLEAR reg > > -- > With best wishes > Dmitry Thanks, Yuanjie
