Enable LT phy for transmitting LFPS during aux-less alpm.
Cc: Jouni Högander <[email protected]>
Signed-off-by: Animesh Manna <[email protected]>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 5 ++-
drivers/gpu/drm/i915/display/intel_lt_phy.c | 35 +++++++++++++++++++
drivers/gpu/drm/i915/display/intel_lt_phy.h | 2 ++
.../gpu/drm/i915/display/intel_lt_phy_regs.h | 3 ++
4 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c
b/drivers/gpu/drm/i915/display/intel_ddi.c
index 733ef4559131..f6450ebea2a8 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3781,7 +3781,10 @@ static void mtl_ddi_prepare_link_retrain(struct intel_dp
*intel_dp,
* ii. Enable MAC Transmits LFPS in the "PHY Common Control 0" PIPE
* register
*/
- intel_lnl_mac_transmit_lfps(encoder, crtc_state);
+ if (HAS_LT_PHY(display))
+ intel_xe3plpd_mac_transmit_lfps(encoder, crtc_state);
+ else
+ intel_lnl_mac_transmit_lfps(encoder, crtc_state);
}
static void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp,
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index af48d6cde226..87659a9d9847 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -7,6 +7,7 @@
#include "i915_reg.h"
#include "i915_utils.h"
+#include "intel_alpm.h"
#include "intel_cx0_phy.h"
#include "intel_cx0_phy_regs.h"
#include "intel_ddi.h"
@@ -1998,3 +1999,37 @@ void intel_xe3plpd_pll_disable(struct intel_encoder
*encoder)
intel_lt_phy_pll_disable(encoder);
}
+
+/*
+ * According to HAS we need to enable MAC Transmitting LFPS in the "PHY Common
+ * Control 0" PIPE register in case of AUX Less ALPM is going to be used. This
+ * function is doing that and is called by link retrain sequence.
+ */
+void intel_xe3plpd_mac_transmit_lfps(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state)
+{
+ intel_wakeref_t wakeref;
+ int i;
+ u8 owned_lane_mask;
+
+ if (!intel_alpm_is_alpm_aux_less(enc_to_intel_dp(encoder), crtc_state))
+ return;
+
+ owned_lane_mask = intel_lt_phy_get_owned_lane_mask(encoder);
+
+ wakeref = intel_lt_phy_transaction_begin(encoder);
+
+ for (i = 0; i < 4; i++) {
+ int tx = i % 2 + 1;
+ u8 lane_mask = i < 2 ? INTEL_LT_PHY_LANE0 : INTEL_LT_PHY_LANE1;
+
+ if (!(owned_lane_mask & lane_mask))
+ continue;
+
+ intel_lt_phy_rmw(encoder, lane_mask, LT_PHY_CMN_CTL(tx, 0),
+ LT_PHY_CMN_LFPS_ENABLE,
+ LT_PHY_CMN_LFPS_ENABLE, MB_WRITE_COMMITTED);
+ }
+
+ intel_lt_phy_transaction_end(encoder, wakeref);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h
b/drivers/gpu/drm/i915/display/intel_lt_phy.h
index a538d4c69210..7391dd7252d7 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h
@@ -38,6 +38,8 @@ void intel_lt_phy_pll_state_verify(struct intel_atomic_state
*state,
void intel_xe3plpd_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
void intel_xe3plpd_pll_disable(struct intel_encoder *encoder);
+void intel_xe3plpd_mac_transmit_lfps(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state);
#define HAS_LT_PHY(display) (DISPLAY_VER(display) >= 35)
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
index 9223487d764e..8a19b7cb59dc 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy_regs.h
@@ -36,6 +36,9 @@
#define LT_PHY_TXY_CTL10_MAC(idx) _MMIO(LT_PHY_TXY_CTL10(idx))
#define LT_PHY_TX_LANE_ENABLE REG_BIT8(0)
+#define LT_PHY_CMN_CTL(idx, control) (0x800 + (0x200 * ((idx) - 1)) +
(control))
+#define LT_PHY_CMN_LFPS_ENABLE REG_BIT8(1)
+
/* LT Phy Vendor Register */
#define LT_PHY_VDR_0_CONFIG 0xC02
#define LT_PHY_VDR_DP_PLL_ENABLE REG_BIT(7)
--
2.29.0
