On Wed, 05 Nov 2025, Uma Shankar <[email protected]> wrote: > From: Chaitanya Kumar Borah <[email protected]> > > Add registers needed to program 3D LUT > > BSpec: 69378, 69379, 69380 > > Signed-off-by: Chaitanya Kumar Borah <[email protected]> > Signed-off-by: Uma Shankar <[email protected]> > --- > .../i915/display/skl_universal_plane_regs.h | 26 +++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > index 4d71d07e90ff..88b4c6c57054 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h > @@ -520,6 +520,32 @@ > #define PLANE_MIN_DBUF_BLOCKS(val) > REG_FIELD_PREP(PLANE_MIN_DBUF_BLOCKS_MASK, (val)) > #define PLANE_INTERIM_DBUF_BLOCKS_MASK REG_GENMASK(11, 0) > #define PLANE_INTERIM_DBUF_BLOCKS(val) > REG_FIELD_PREP(PLANE_INTERIM_DBUF_BLOCKS_MASK, (val)) > +/* 3D LUT */ > +#define _LUT_3D_CTL_A 0x490A4 > +#define _LUT_3D_CTL_B 0x491A4 > +#define LUT_3D_ENABLE REG_BIT(31) > +#define LUT_3D_READY REG_BIT(30) > +#define LUT_3D_BINDING_MASK REG_GENMASK(23, 22) > +#define LUT_3D_BIND_PIPE REG_FIELD_PREP(LUT_3D_BINDING_MASK, 0) > +#define LUT_3D_BIND_PLANE_1 > REG_FIELD_PREP(LUT_3D_BINDING_MASK, 1) > +#define LUT_3D_BIND_PLANE_2 > REG_FIELD_PREP(LUT_3D_BINDING_MASK, 2) > +#define LUT_3D_BIND_PLANE_3 > REG_FIELD_PREP(LUT_3D_BINDING_MASK, 3) > +#define _LUT_3D_INDEX_A 0x490A8 > +#define _LUT_3D_INDEX_B 0x491A8 > +#define LUT_3D_AUTO_INCREMENT REG_BIT(13) > +#define LUT_3D_INDEX_VALUE_MASK REG_GENMASK(12, 0) > +#define LUT_3D_INDEX_VALUE(x) > REG_FIELD_PREP(LUT_3D_INDEX_VALUE_MASK, (x)) > +#define _LUT_3D_DATA_A 0x490AC > +#define _LUT_3D_DATA_B 0x491AC > +#define LUT_3D_DATA_RED_MASK REG_GENMASK(29, 20) > +#define LUT_3D_DATA_GREEN_MASK REG_GENMASK(19, 10) > +#define LUT_3D_DATA_BLUE_MASK REG_GENMASK(9, 0) > +#define LUT_3D_DATA_RED(x) REG_FIELD_PREP(LUT_3D_DATA_RED_MASK, > (x)) > +#define LUT_3D_DATA_GREEN(x) > REG_FIELD_PREP(LUT_3D_DATA_GREEN_MASK, (x)) > +#define LUT_3D_DATA_BLUE(x) > REG_FIELD_PREP(LUT_3D_DATA_BLUE_MASK, (x)) > +#define LUT_3D_CTL(pipe) _MMIO_PIPE(pipe, _LUT_3D_CTL_A, _LUT_3D_CTL_B) > +#define LUT_3D_INDEX(pipe) _MMIO_PIPE(pipe, _LUT_3D_INDEX_A, > _LUT_3D_INDEX_B) > +#define LUT_3D_DATA(pipe) _MMIO_PIPE(pipe, _LUT_3D_DATA_A, _LUT_3D_DATA_B)
The regs go before their contents. For the umpteenth time, please read the big comment near the top of i915_reg.h. > > /* tgl+ */ > #define _SEL_FETCH_PLANE_CTL_1_A 0x70890 -- Jani Nikula, Intel
