> Subject: [v6 16/16] drm/i915/color: Enable Plane Color Pipelines > > Expose color pipeline and add ability to program it. > > v2: Set bit to enable multisegmented lut > v3: s/drm_color_lut_32/drm_color_lut32 (Simon) > v4: - Fix dsb programming > - Remove multi-segment LUT, they will be added in later patches > - Add pipeline only to TGL+ > - Code Refactor > > Signed-off-by: Chaitanya Kumar Borah <[email protected]> > Signed-off-by: Uma Shankar <[email protected]>
LGTM, Reviewed-by: Suraj Kandpal <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_display.c | 5 ++++- > .../drm/i915/display/skl_universal_plane.c | 21 +++++++++++++++++++ > 2 files changed, 25 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index 42ec78798666..ea898a0bdefb 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -7284,6 +7284,7 @@ static void intel_atomic_dsb_finish(struct > intel_atomic_state *state, > struct intel_display *display = to_intel_display(state); > struct intel_crtc_state *new_crtc_state = > intel_atomic_get_new_crtc_state(state, crtc); > + unsigned int size = new_crtc_state->plane_color_changed ? 8192 : > 1024; > > if (!new_crtc_state->use_flipq && > !new_crtc_state->use_dsb && > @@ -7294,10 +7295,12 @@ static void intel_atomic_dsb_finish(struct > intel_atomic_state *state, > * Rough estimate: > * ~64 registers per each plane * 8 planes = 512 > * Double that for pipe stuff and other overhead. > + * ~4913 registers for 3DLUT > + * ~200 color registers * 3 HDR planes > */ > new_crtc_state->dsb_commit = intel_dsb_prepare(state, crtc, > INTEL_DSB_0, > new_crtc_state->use_dsb > || > - new_crtc_state- > >use_flipq ? 1024 : 16); > + new_crtc_state- > >use_flipq ? size : 16); > if (!new_crtc_state->dsb_commit) { > new_crtc_state->use_flipq = false; > new_crtc_state->use_dsb = false; > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c > b/drivers/gpu/drm/i915/display/skl_universal_plane.c > index ba1bf0bd4c55..f58d17842c24 100644 > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c > @@ -11,6 +11,8 @@ > > #include "pxp/intel_pxp.h" > #include "intel_bo.h" > +#include "intel_color.h" > +#include "intel_color_pipeline.h" > #include "intel_de.h" > #include "intel_display_irq.h" > #include "intel_display_regs.h" > @@ -1276,6 +1278,18 @@ static u32 glk_plane_color_ctl(const struct > intel_plane_state *plane_state) > if (plane_state->force_black) > plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE; > > + if (plane_state->hw.degamma_lut) > + plane_color_ctl |= > PLANE_COLOR_PRE_CSC_GAMMA_ENABLE; > + > + if (plane_state->hw.ctm) > + plane_color_ctl |= PLANE_COLOR_PLANE_CSC_ENABLE; > + > + if (plane_state->hw.gamma_lut) { > + plane_color_ctl &= > ~PLANE_COLOR_PLANE_GAMMA_DISABLE; > + if (drm_color_lut32_size(plane_state->hw.gamma_lut) != 32) > + plane_color_ctl |= > PLANE_COLOR_POST_CSC_GAMMA_MULTSEG_ENABLE; > + } > + > return plane_color_ctl; > } > > @@ -1557,6 +1571,8 @@ icl_plane_update_noarm(struct intel_dsb *dsb, > plane_color_ctl = plane_state->color_ctl | > glk_plane_color_ctl_crtc(crtc_state); > > + intel_color_plane_program_pipeline(dsb, plane_state); > + > /* The scaler will handle the output position */ > if (plane_state->scaler_id >= 0) { > crtc_x = 0; > @@ -1658,6 +1674,8 @@ icl_plane_update_arm(struct intel_dsb *dsb, > > icl_plane_update_sel_fetch_arm(dsb, plane, crtc_state, plane_state); > > + intel_color_plane_commit_arm(dsb, plane_state); > + > /* > * In order to have FBC for fp16 formats pixel normalizer block must be > * active. Check if pixel normalizer block need to be enabled for FBC. > @@ -3001,6 +3019,9 @@ skl_universal_plane_create(struct intel_display > *display, > DRM_COLOR_YCBCR_BT709, > > DRM_COLOR_YCBCR_LIMITED_RANGE); > > + if (DISPLAY_VER(display) >= 12) > + intel_color_pipeline_plane_init(&plane->base, pipe); > + > drm_plane_create_alpha_property(&plane->base); > drm_plane_create_blend_mode_property(&plane->base, > > BIT(DRM_MODE_BLEND_PIXEL_NONE) | > -- > 2.50.1
