> Subject: [v6 12/16] drm/i915/color: Program Pre-CSC registers > > Add callback to program Pre-CSC LUT for TGL and beyond > > v2: Add DSB support > v3: Add support for single segment 1D LUT color op > v4: > - s/drm_color_lut_32/drm_color_lut32/ (Simon) > - Change commit message (Suraj) > - Improve comments (Suraj) > - Remove multisegmented programming, to be added later > - Remove dead code for SDR planes, add when needed >
Bspec link here, also if you can provide it as a reply so that I can verify the sequence for these writes Regards, Suraj Kandpal > Signed-off-by: Uma Shankar <[email protected]> > Signed-off-by: Chaitanya Kumar Borah <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_color.c | 61 ++++++++++++++++++++++ > 1 file changed, 61 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c > b/drivers/gpu/drm/i915/display/intel_color.c > index 83b0cb519e44..ac15a8b2c6b3 100644 > --- a/drivers/gpu/drm/i915/display/intel_color.c > +++ b/drivers/gpu/drm/i915/display/intel_color.c > @@ -3942,6 +3942,66 @@ xelpd_load_plane_csc_matrix(struct intel_dsb > *dsb, > ctm_to_twos_complement(input[11], 0, 12)); } > > +static void > +xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb, > + const struct intel_plane_state *plane_state) { > + struct intel_display *display = to_intel_display(plane_state); > + const struct drm_plane_state *state = &plane_state->uapi; > + enum pipe pipe = to_intel_plane(state->plane)->pipe; > + enum plane_id plane = to_intel_plane(state->plane)->id; > + const struct drm_color_lut32 *pre_csc_lut = plane_state- > >hw.degamma_lut->data; > + u32 i, lut_size; > + > + if (icl_is_hdr_plane(display, plane)) { > + lut_size = 128; > + > + intel_de_write_dsb(display, dsb, > + PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, > plane, 0), > + PLANE_PAL_PREC_AUTO_INCREMENT); > + > + if (pre_csc_lut) { > + for (i = 0; i < lut_size; i++) { > + u32 lut_val = > drm_color_lut32_extract(pre_csc_lut[i].green, 24); > + > + intel_de_write_dsb(display, dsb, > + > PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), > + lut_val); > + } > + > + /* Program the max register to clamp values > 1.0. */ > + /* TODO: Restrict to 0x7ffffff */ > + do { > + intel_de_write_dsb(display, dsb, > + > PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), > + (1 << 24)); > + } while (i++ > 130); > + } else { > + for (i = 0; i < lut_size; i++) { > + u32 v = (i * ((1 << 24) - 1)) / (lut_size - 1); > + > + intel_de_write_dsb(display, dsb, > + > PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), v); > + } > + > + do { > + intel_de_write_dsb(display, dsb, > + > PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), > + 1 << 24); > + } while (i++ < 130); > + } > + > + intel_de_write_dsb(display, dsb, > PLANE_PRE_CSC_GAMC_INDEX_ENH(pipe, plane, 0), 0); > + } > +} > + > +static void > +xelpd_plane_load_luts(struct intel_dsb *dsb, const struct > +intel_plane_state *plane_state) { > + if (plane_state->hw.degamma_lut) > + xelpd_program_plane_pre_csc_lut(dsb, plane_state); } > + > static const struct intel_color_funcs chv_color_funcs = { > .color_check = chv_color_check, > .color_commit_arm = i9xx_color_commit_arm, @@ -3990,6 +4050,7 > @@ static const struct intel_color_funcs tgl_color_funcs = { > .read_csc = icl_read_csc, > .get_config = skl_get_config, > .load_plane_csc_matrix = xelpd_load_plane_csc_matrix, > + .load_plane_luts = xelpd_plane_load_luts, > }; > > static const struct intel_color_funcs icl_color_funcs = { > -- > 2.50.1
