When the initial drivers were submitted, some of the timing was hard coded and
did not allow for any MIPI-DSI panel to be attached.
In general, panels or bridges can only be supported if MIPI-DSI lanes were 4.
If the number of lanes were 3,2,1, the math no longer works out.
A new API was created for the clock driver because the behaivior of the clock
driver depends on DPI vs MIPI, the bpp, and the number of MIPI lanes.
Testing:
* RZ/G2L SMARC (MIPI-DSI to HDMI bridge, lanes = 4)
* RZ/G2L-SBC (MIPI-DSI to LCD panel, lanes = 2)
* RZ/G2UL SMARC (DPI to HDMI bridge)
* Multiple monitors, multiple resolutions
* repo: git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git
* branch: renesas-clk
base-commit: 5fb2f67341bd4b7c482f2bbda6b78244a51c3923
Depends-on:
"clk: renesas: rzg2l: Fix intin variable size"
https://lore.kernel.org/all/[email protected]
"clk: renesas: rzg2l: Select correct div round macro"
https://lore.kernel.org/all/[email protected]
Chris Brandt (2):
clk: renesas: rzg2l: Remove DSI clock rate restrictions
drm: renesas: rz-du: mipi_dsi: Set DSI divider
drivers/clk/renesas/rzg2l-cpg.c | 170 +++++++++++++++---
.../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 17 +-
include/linux/clk/renesas.h | 11 ++
3 files changed, 168 insertions(+), 30 deletions(-)
--
2.50.1
