Hi Chris, On Mon, 24 Nov 2025 08:10:03 -0500 Chris Brandt <[email protected]> wrote:
> Before the MIPI DSI clock source can be configured, the target divide > ratio needs to be known. > > Signed-off-by: Chris Brandt <[email protected]> > Reviewed-by: Biju Das <[email protected]> > Tested-by: Biju Das <[email protected]> Reviewed-by: Hugo Villeneuve <[email protected]> Tested-by: Hugo Villeneuve <[email protected]> > > --- > v1->v2: > - Add spaces around '/' in comments > - Add target argument in new API > > v2->v3: > - Add missing period in comment (Hugo) > - Changed '1' to 'PLL5_TARGET_DSI' (Hugo) > - Added Reviewed-by and Tested-by (Biju) > > v3->v4: > - Fixed up the comments > - Fixed the match for the divider to set (was missing a * 2) > > v4->v5: > - Rename patch title (Hugo) > - Add bpp varable for easy reuse (Hugo) > > v5->v6: > - Remove clock diagram that was wrong (Chris) > --- > drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 17 ++++++++++++++++- > 1 file changed, 16 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > index 3b52dfc0ea1e..bee2cc711afd 100644 > --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c > @@ -7,6 +7,7 @@ > > #include <linux/bitfield.h> > #include <linux/clk.h> > +#include <linux/clk/renesas.h> > #include <linux/delay.h> > #include <linux/dma-mapping.h> > #include <linux/io.h> > @@ -692,6 +693,7 @@ static int rzg2l_mipi_dsi_host_attach(struct > mipi_dsi_host *host, > struct mipi_dsi_device *device) > { > struct rzg2l_mipi_dsi *dsi = host_to_rzg2l_mipi_dsi(host); > + int bpp; > int ret; > > if (device->lanes > dsi->num_data_lanes) { > @@ -701,7 +703,8 @@ static int rzg2l_mipi_dsi_host_attach(struct > mipi_dsi_host *host, > return -EINVAL; > } > > - switch (mipi_dsi_pixel_format_to_bpp(device->format)) { > + bpp = mipi_dsi_pixel_format_to_bpp(device->format); > + switch (bpp) { > case 24: > break; > case 18: > @@ -732,6 +735,18 @@ static int rzg2l_mipi_dsi_host_attach(struct > mipi_dsi_host *host, > > drm_bridge_add(&dsi->bridge); > > + /* > + * Report the required division ratio setting for the MIPI clock > dividers. > + * > + * vclk * bpp = hsclk * 8 * num_lanes > + * > + * vclk * DSI_AB_divider = hsclk * 16 > + * > + * which simplifies to... > + * DSI_AB_divider = bpp * 2 / num_lanes > + */ > + rzg2l_cpg_dsi_div_set_divider(bpp * 2 / dsi->lanes, PLL5_TARGET_DSI); > + > return 0; > } > > -- > 2.50.1 > > -- Hugo Villeneuve
