On Mon, Jan 5, 2026 at 10:13 AM Icenowy Zheng <[email protected]> wrote: > > 在 2026-01-05星期一的 09:46 -0600，Rob Herring写道： > > On Thu, Dec 25, 2025 at 12:11:58AM +0800, Icenowy Zheng wrote: > > > From: Icenowy Zheng <[email protected]> > > > > > > Verisilicon has a series of display controllers prefixed with DC > > > and > > > with self-identification facility like their GC series GPUs. > > > > > > Add a device tree binding for it. > > > > > > Depends on the specific DC model, it can have either one or two > > > display > > > outputs, and each display output could be set to DPI signal or "DP" > > > signal (which seems to be some plain parallel bus to HDMI > > > controllers). > > > > > > Signed-off-by: Icenowy Zheng <[email protected]> > > > Signed-off-by: Icenowy Zheng <[email protected]> > > > --- > > > Changes in v4: > > > - Added a comment for "verisilicon,dc" that says the ID/revision is > > > discoverable via registers. > > > - Removed clock minItems constraint w/o specific compatible > > > strings. > > > > > > Changes in v3: > > > - Added SoC-specific compatible string, and arm the binding with > > > clock / > > > port checking for the specific SoC (with a 2-output DC). > > > > > > Changes in v2: > > > - Fixed misspelt "versilicon" in title. > > > - Moved minItems in clock properties to be earlier than items. > > > - Re-aligned multi-line clocks and resets in example. > > > > > > .../bindings/display/verisilicon,dc.yaml | 144 > > > ++++++++++++++++++ > > > 1 file changed, 144 insertions(+) > > > create mode 100644 > > > Documentation/devicetree/bindings/display/verisilicon,dc.yaml > > > > > > diff --git > > > a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml > > > b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml > > > new file mode 100644 > > > index 0000000000000..fe64cc1466690 > > > --- /dev/null > > > +++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml > > > @@ -0,0 +1,144 @@ > > > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > > > +%YAML 1.2 > > > +--- > > > +$id: http://devicetree.org/schemas/display/verisilicon,dc.yaml# > > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > > + > > > +title: Verisilicon DC-series display controllers > > > + > > > +maintainers: > > > + - Icenowy Zheng <[email protected]> > > > + > > > +properties: > > > + $nodename: > > > + pattern: "^display@[0-9a-f]+$" > > > + > > > + compatible: > > > + items: > > > + - enum: > > > + - thead,th1520-dc8200 > > > + - const: verisilicon,dc # DC IPs have discoverable > > > ID/revision registers > > > + > > > + reg: > > > + maxItems: 1 > > > + > > > + interrupts: > > > + maxItems: 1 > > > + > > > + clocks: > > > + items: > > > + - description: DC Core clock > > > + - description: DMA AXI bus clock > > > + - description: Configuration AHB bus clock > > > + - description: Pixel clock of output 0 > > > + - description: Pixel clock of output 1 > > > + > > > + clock-names: > > > + items: > > > + - const: core > > > + - const: axi > > > + - const: ahb > > > + - const: pix0 > > > + - const: pix1 > > > + > > > + resets: > > > + items: > > > + - description: DC Core reset > > > + - description: DMA AXI bus reset > > > + - description: Configuration AHB bus reset > > > + > > > + reset-names: > > > + items: > > > + - const: core > > > + - const: axi > > > + - const: ahb > > > + > > > + ports: > > > + $ref: /schemas/graph.yaml#/properties/ports > > > + > > > + properties: > > > + port@0: > > > + $ref: /schemas/graph.yaml#/properties/port > > > + description: The first output channel , endpoint 0 should > > > be > > > > No space before comma. Or perhaps should be a period instead. > > Well I don't know why I inserted such a space, will remove it. > > > > > > > > + used for DPI format output and endpoint 1 should be used > > > + for DP format output. > > > + > > > + port@1: > > > + $ref: /schemas/graph.yaml#/properties/port > > > + description: The second output channel if the DC variant > > > + supports. Follow the same endpoint addressing rule with > > > + the first port. > > > + > > > + required: > > > + - port@0 > > > + > > > +required: > > > + - compatible > > > + - reg > > > + - interrupts > > > + - clocks > > > + - clock-names > > > + - ports > > > + > > > +allOf: > > > + - if: > > > + properties: > > > + compatible: > > > + contains: > > > + const: thead,th1520-dc8200 > > > + then: > > > + properties: > > > + clocks: > > > + minItems: 5 > > > > That's already implicitly the min. Perhaps you wanted 'minItems: 4' > > on > > the clocks and clock-names definitions for versions with only 1 > > output? > > Previously I specified minItems: 4 in the general part, however this > does not play well when some of core/axi/ahb clocks are not present.
I don't understand. That would only make pix1 optional. There of course is no way we can check that 'clocks' entries are pointing to the correct clocks. > > > + ports: > > > + required: > > > + - port@0 > > > + - port@1 > > > > It is valid to omit these if the output is present, but unused. > > Well this sounds reasonable, although my driver does not play well if > only a port@1 is defined w/o port@0 . Sounds like your driver should be fixed. > Considering the previous two snippets, should I just remove this if > part? I would, yes. Rob
