On Mon, Jan 19, 2026 at 12:08:07PM +0100, Konrad Dybcio wrote:
> On 1/19/26 9:17 AM, Dmitry Baryshkov wrote:
> > Code in dpu_hw_sspp_setup_format() doesn't handle UBWC versions bigger
> > than 4.0. Replace switch-case with if-else checks, making sure that the
> > register is initialized on UBWC 5.x (and later) hosts.
> >
> > Fixes: c2577fc1740d ("drm/msm/dpu: Add support for SM8750")
> > Tested-by: Val Packett <[email protected]> # x1e80100-dell-latitude-7455
> > Signed-off-by: Dmitry Baryshkov <[email protected]>
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 44
> > +++++++++++++++--------------
> > 1 file changed, 23 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> > b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> > index a99e33230514..80a9fb76b139 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c
> > @@ -279,6 +279,7 @@ static void dpu_hw_sspp_setup_format(struct dpu_sw_pipe
> > *pipe,
> >
> > if (fmt->fetch_mode != MDP_FETCH_LINEAR) {
> > u32 hbb = ctx->ubwc->highest_bank_bit - 13;
> > + u32 ctrl_val;
> >
> > if (MSM_FORMAT_IS_UBWC(fmt))
> > opmode |= MDSS_MDP_OP_BWC_EN;
> > @@ -286,30 +287,31 @@ static void dpu_hw_sspp_setup_format(struct
> > dpu_sw_pipe *pipe,
> > DPU_REG_WRITE(c, SSPP_FETCH_CONFIG,
> > DPU_FETCH_CONFIG_RESET_VALUE |
> > hbb << 18);
> > - switch (ctx->ubwc->ubwc_enc_version) {
> > - case UBWC_1_0:
> > +
> > + if (ctx->ubwc->ubwc_enc_version == UBWC_1_0) {
> > fast_clear = fmt->alpha_enable ? BIT(31) : 0;
> > - DPU_REG_WRITE(c, ubwc_static_ctrl_off,
> > - fast_clear | (ctx->ubwc->ubwc_swizzle &
> > 0x1) |
> > - BIT(8) |
> > - (hbb << 4));
> > - break;
> > - case UBWC_2_0:
> > + ctrl_val = fast_clear | (ctx->ubwc->ubwc_swizzle & 0x1)
> > |
> > + BIT(8) | (hbb << 4);
> > + } else if (ctx->ubwc->ubwc_enc_version == UBWC_2_0) {
> > fast_clear = fmt->alpha_enable ? BIT(31) : 0;
> > - DPU_REG_WRITE(c, ubwc_static_ctrl_off,
> > - fast_clear | (ctx->ubwc->ubwc_swizzle) |
> > - (hbb << 4));
> > - break;
> > - case UBWC_3_0:
> > - DPU_REG_WRITE(c, ubwc_static_ctrl_off,
> > - BIT(30) | (ctx->ubwc->ubwc_swizzle) |
> > - (hbb << 4));
> > - break;
> > - case UBWC_4_0:
> > - DPU_REG_WRITE(c, ubwc_static_ctrl_off,
> > - MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30));
> > - break;
> > + ctrl_val = fast_clear | ctx->ubwc->ubwc_swizzle | (hbb
> > << 4);
> > + } else if (ctx->ubwc->ubwc_enc_version == UBWC_3_0) {
> > + ctrl_val = BIT(30) | (ctx->ubwc->ubwc_swizzle) | (hbb
> > << 4);
> > + } else if (ctx->ubwc->ubwc_enc_version == UBWC_4_0) {
> > + ctrl_val = MSM_FORMAT_IS_YUV(fmt) ? 0 : BIT(30);
> > + } else if (ctx->ubwc->ubwc_enc_version <= UBWC_6_0) {
> > + if (MSM_FORMAT_IS_YUV(fmt))
> > + ctrl_val = 0;
> > + else if (MSM_FORMAT_IS_DX(fmt)) /* or FP16, but it's
> > unsupported */
> > + ctrl_val = BIT(30);
> > + else
> > + ctrl_val = BIT(30) | BIT(31);
>
> Can we name these magic bits?
I will raise the question internally. In general, I'd like to start
shifting towards generated reg descriptions, but it will take some time
to implement.
>
> There's 2 more bitfields that I see downstream sets here (but it
> doesn't claim to support UBWC6)..
For the formats which we don't support upstream. I'll add a comment
here (and I probably should send another iteration anyway, fixing the
error register too).
--
With best wishes
Dmitry
