The MIPI DSI interface on the RZ/G3E SoC is nearly identical to that of the RZ/V2H(P) SoC, except that this have 2 input port and can use vclk1 or vclk2 as DSI Video clock, depending on the selected port.
To accommodate these differences, a SoC-specific `renesas,r9a09g047-mipi-dsi` compatible string has been added for the RZ/G3E SoC. Signed-off-by: Tommaso Merciai <[email protected]> --- v1->v2: - Removed oneOf from clocks property, which is no sufficient to differentiate between RZ/G3E, RZ/V2H(P) and RZ/G2L. In particular both RZ/G3E and RZ/G2L have 6 clocks with different meanings. - Use the already exist vclk instead of vclk1 for RZ/G3E DSI bindings. - Updated the allOf section accordingly. v2->v3: - No changes. v3->v4: - No changes. .../bindings/display/bridge/renesas,dsi.yaml | 144 +++++++++++++----- 1 file changed, 109 insertions(+), 35 deletions(-) diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml index c20625b8425e..00ef279129fd 100644 --- a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml @@ -28,6 +28,7 @@ properties: - const: renesas,r9a09g057-mipi-dsi - enum: + - renesas,r9a09g047-mipi-dsi # RZ/G3E - renesas,r9a09g057-mipi-dsi # RZ/V2H(P) reg: @@ -54,20 +55,8 @@ properties: - const: debug clocks: - oneOf: - - items: - - description: DSI D-PHY PLL multiplied clock - - description: DSI D-PHY system clock - - description: DSI AXI bus clock - - description: DSI Register access clock - - description: DSI Video clock - - description: DSI D-PHY Escape mode transmit clock - - items: - - description: DSI D-PHY PLL reference clock - - description: DSI AXI bus clock - - description: DSI Register access clock - - description: DSI Video clock - - description: DSI D-PHY Escape mode transmit clock + minItems: 5 + maxItems: 6 clock-names: oneOf: @@ -78,12 +67,14 @@ properties: - const: pclk - const: vclk - const: lpclk - - items: + - minItems: 5 + items: - const: pllrefclk - const: aclk - const: pclk - const: vclk - const: lpclk + - const: vclk2 resets: oneOf: @@ -136,13 +127,6 @@ properties: - const: 3 - const: 4 - required: - - data-lanes - - required: - - port@0 - - port@1 - required: - compatible - reg @@ -164,33 +148,123 @@ allOf: properties: compatible: contains: - const: renesas,r9a09g057-mipi-dsi + const: renesas,r9a09g047-mipi-dsi then: properties: - clocks: - maxItems: 5 + ports: + properties: + port@0: + description: DSI input port 0 + port@1: + description: DSI input port 1 + properties: + endpoint: + properties: + data-lanes: false + port@2: + description: DSI output port + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: array of physical DSI data lane indexes. + minItems: 1 + items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + required: + - data-lanes + + required: + - port@0 + - port@1 + - port@2 + else: + properties: + ports: + properties: + port@0: true + port@1: + properties: + endpoint: + properties: + data-lanes: true + required: + - data-lanes + + required: + - port@0 + - port@1 + - if: + properties: + compatible: + contains: + const: renesas,rzg2l-mipi-dsi + then: + properties: + clocks: + items: + - description: DSI D-PHY PLL multiplied clock + - description: DSI D-PHY system clock + - description: DSI AXI bus clock + - description: DSI Register access clock + - description: DSI Video clock + - description: DSI D-PHY Escape mode transmit clock clock-names: - maxItems: 5 + minItems: 6 + resets: + minItems: 3 + reset-names: + minItems: 3 + - if: + properties: + compatible: + contains: + const: renesas,r9a09g047-mipi-dsi + then: + properties: + clocks: + items: + - description: DSI D-PHY PLL reference clock + - description: DSI AXI bus clock + - description: DSI Register access clock + - description: DSI Video clock + - description: DSI D-PHY Escape mode transmit clock + - description: DSI Video clock (2nd input clock) + clock-names: + minItems: 6 resets: maxItems: 2 - reset-names: maxItems: 2 - else: + + - if: + properties: + compatible: + contains: + const: renesas,r9a09g057-mipi-dsi + then: properties: clocks: - minItems: 6 - + items: + - description: DSI D-PHY PLL reference clock + - description: DSI AXI bus clock + - description: DSI Register access clock + - description: DSI Video clock + - description: DSI D-PHY Escape mode transmit clock clock-names: - minItems: 6 - + maxItems: 5 resets: - minItems: 3 - + maxItems: 2 reset-names: - minItems: 3 + maxItems: 2 examples: - | -- 2.43.0
