On Mon, 02 Feb 2026 12:57:41 +0100, Tommaso Merciai wrote: > The MIPI DSI interface on the RZ/G3E SoC is nearly identical to that of > the RZ/V2H(P) SoC, except that this have 2 input port and can use vclk1 > or vclk2 as DSI Video clock, depending on the selected port. > > To accommodate these differences, a SoC-specific > `renesas,r9a09g047-mipi-dsi` compatible string has been added for the > RZ/G3E SoC. > > Signed-off-by: Tommaso Merciai <[email protected]> > --- > v1->v2: > - Removed oneOf from clocks property, which is no sufficient to > differentiate between RZ/G3E, RZ/V2H(P) and RZ/G2L. > In particular both RZ/G3E and RZ/G2L have 6 clocks with different > meanings. > - Use the already exist vclk instead of vclk1 for RZ/G3E DSI bindings. > - Updated the allOf section accordingly. > > v2->v3: > - No changes. > > v3->v4: > - No changes. > > .../bindings/display/bridge/renesas,dsi.yaml | 144 +++++++++++++----- > 1 file changed, 109 insertions(+), 35 deletions(-) >
Reviewed-by: Rob Herring (Arm) <[email protected]>
