The RZ/G3E Soc has 2 LCD controller (LCDC), contain a Frame Compression Processor (FCPVD), a Video Signal Processor (VSPD), Video Signal Processor (VSPD), and Display Unit (DU).
- LCDC0 supports DSI and LVDS (single or dual-channel) outputs. - LCDC1 supports DSI, LVDS (single-channel), and RGB outputs. Add new SoC-specific compatible string 'renesas,r9a09g047-du'. Signed-off-by: Tommaso Merciai <[email protected]> --- v4->v5: - Dropped renesas,id property and updated bindings accordingly. v2->v3: - No changes. v2->v3: - No changes. v1->v2: - Use single compatible string instead of multiple compatible strings for the two DU instances, leveraging a 'renesas,id' property to differentiate between DU0 and DU1. - Updated commit message accordingly. .../bindings/display/renesas,rzg2l-du.yaml | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml index 2cc66dcef870..be50b153d651 100644 --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml @@ -20,6 +20,7 @@ properties: - enum: - renesas,r9a07g043u-du # RZ/G2UL - renesas,r9a07g044-du # RZ/G2{L,LC} + - renesas,r9a09g047-du # RZ/G3E - renesas,r9a09g057-du # RZ/V2H(P) - items: - enum: @@ -137,6 +138,27 @@ allOf: required: - port@0 + - if: + properties: + compatible: + contains: + const: renesas,r9a09g047-du + then: + properties: + ports: + properties: + port@0: + description: DSI + port@1: + description: LVDS Channel 0 + port@2: + description: LVDS Channel 1 + port@3: + description: DPAD + + required: + - port@0 + - port@1 examples: # RZ/G2L DU -- 2.43.0
