> -----Original Message-----
> From: Hogander, Jouni <[email protected]>
> Sent: Monday, March 23, 2026 6:43 PM
> To: [email protected]; [email protected]; Manna,
> Animesh <[email protected]>; [email protected]
> Cc: Murthy, Arun R <[email protected]>; Nikula, Jani
> <[email protected]>; Deak, Imre <[email protected]>
> Subject: Re: [PATCH v8 2/3] drm/i915/display: Add hook to check
> optimization support for Intel platforms
>
> On Mon, 2026-03-23 at 15:04 +0200, Hogander, Jouni wrote:
> > On Wed, 2026-03-18 at 14:26 +0530, Animesh Manna wrote:
> > > Add a hook that uses the drm core tunneling function to check
> > > whether panel replay bandwidth optimization support is present.
> > >
> > > v2: Move DISPLAY_VER() check to
> > > intel_dp_tunnel_pr_optimization_supported(). [Jouni]
> > >
> > > Signed-off-by: Animesh Manna <[email protected]>
> >
> > Reviewed-by: Jouni Högander <[email protected]>
> >
> > > ---
> > > drivers/gpu/drm/i915/display/intel_dp_tunnel.c | 18
> > > ++++++++++++++++++
> > > drivers/gpu/drm/i915/display/intel_dp_tunnel.h | 6 ++++++
> > > 2 files changed, 24 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > index 1fd1ac8d556d..b81ac9a2d727 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.c
> > > @@ -296,6 +296,24 @@ bool
> > > intel_dp_tunnel_bw_alloc_is_enabled(struct
> > > intel_dp *intel_dp)
> > > return drm_dp_tunnel_bw_alloc_is_enabled(intel_dp-
> > > >tunnel);
> > > }
> > >
> > > +/**
> > > + * intel_dp_tunnel_pr_optimization_supported - Query the PR BW
> > > optimization support
> > > + * @intel_dp: DP port object
> > > + *
> > > + * Query whether a DP tunnel supports the PR BW optimization.
> > > + *
> > > + * Returns %true if the BW allocation mode is supported on
> > > @intel_dp.
> > > + */
> > > +bool intel_dp_tunnel_pr_optimization_supported(struct intel_dp
> > > *intel_dp)
> > > +{
> > > + struct intel_display *display =
> > > to_intel_display(intel_dp);
> > > +
> > > + if (DISPLAY_VER(display) < 35)
> > > + return false;
>
> Just noticed in Bspec that this is actually supported already on
> DISPLAY_VER() == 30.
This feature moved from PTL to NVL due to limitation from soc side, though
display engine is supporting it.
Regards,
Animesh
>
> BR,
> Jouni Högander
>
> > > +
> > > + return drm_dp_tunnel_pr_optimization_supported(intel_dp-
> > > > tunnel);
> > > +}
> > > +
> > > /**
> > > * intel_dp_tunnel_suspend - Suspend a DP tunnel connected on a
> > > port
> > > * @intel_dp: DP port object
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp_tunnel.h
> > > b/drivers/gpu/drm/i915/display/intel_dp_tunnel.h
> > > index 7f0f720e8dca..03e147736b65 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp_tunnel.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp_tunnel.h
> > > @@ -32,6 +32,7 @@ void intel_dp_tunnel_resume(struct intel_dp
> > > *intel_dp,
> > > void intel_dp_tunnel_suspend(struct intel_dp *intel_dp);
> > >
> > > bool intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp
> > > *intel_dp);
> > > +bool intel_dp_tunnel_pr_optimization_supported(struct intel_dp
> > > *intel_dp);
> > >
> > > void
> > > intel_dp_tunnel_atomic_cleanup_inherited_state(struct
> > > intel_atomic_state *state);
> > > @@ -76,6 +77,11 @@ static inline bool
> > > intel_dp_tunnel_bw_alloc_is_enabled(struct intel_dp *intel_dp
> > > return false;
> > > }
> > >
> > > +static inline bool
> > > intel_dp_tunnel_pr_optimization_supported(struct
> > > intel_dp *intel_dp)
> > > +{
> > > + return false;
> > > +}
> > > +
> > > static inline void
> > > intel_dp_tunnel_atomic_cleanup_inherited_state(struct
> > > intel_atomic_state *state) {}
> > >
> >
