On 3/27/26 1:14 AM, Akhil P Oommen wrote:
> Implement pwrup reglist support and add the necessary register
> configurations to enable IFPC support on A840
>
> Signed-off-by: Akhil P Oommen <[email protected]>
> ---
[...]
> + REG_A8XX_CP_PROTECT_GLOBAL(51),
> + REG_A8XX_CP_PROTECT_GLOBAL(52),
> + REG_A8XX_CP_PROTECT_GLOBAL(53),
> + REG_A8XX_CP_PROTECT_GLOBAL(54),
> + REG_A8XX_CP_PROTECT_GLOBAL(55),
> + REG_A8XX_CP_PROTECT_GLOBAL(56),
> + REG_A8XX_CP_PROTECT_GLOBAL(57),
> + REG_A8XX_CP_PROTECT_GLOBAL(58),
> + REG_A8XX_CP_PROTECT_GLOBAL(59),
> + REG_A8XX_CP_PROTECT_GLOBAL(60),
> + REG_A8XX_CP_PROTECT_GLOBAL(61),
> + REG_A8XX_CP_PROTECT_GLOBAL(62),
53..62 aren't listed by kgsl, but I suppose this is more robust
Similarly for:
SP_CHICKEN_BITS_4
RBBM_PERFCTR_CNTL
The other reglists look OK
[...]
> + for (u32 pipe_id = PIPE_BR; pipe_id <= PIPE_DDE_BV; pipe_id++) {
> + for (i = 0; i < dyn_pwrup_reglist->count; i++) {
> + if (!(dyn_pwrup_reglist->regs[i].pipe & BIT(pipe_id)))
> + continue;
> + *dest++ = A8XX_CP_APERTURE_CNTL_HOST_PIPEID(pipe_id);
> + *dest++ = dyn_pwrup_reglist->regs[i].offset;
> + *dest++ = a8xx_read_pipe_slice(gpu,
> + pipe_id,
> +
> a8xx_get_first_slice(a6xx_gpu),
IDK if the compiler is smart enough to pick it up itself, but
you could do const u32 first_slice = a8xx.. beforehand to save a
couple cycles
[...]
> + if (!a6xx_gpu->pwrup_reglist_emitted) {
> + a8xx_patch_pwrup_reglist(gpu);
> + a6xx_gpu->pwrup_reglist_emitted = true;
Would this flag be better set in the function above?
Konrad
