On 3/27/2026 4:44 PM, Konrad Dybcio wrote: > On 3/27/26 1:14 AM, Akhil P Oommen wrote: >> Add the SKU table in the catalog for A840 GPU. This data helps to pick >> the correct bin from the OPP table based on the speed_bin fuse value. >> >> Signed-off-by: Akhil P Oommen <[email protected]> >> --- >> drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 6 ++++++ >> 1 file changed, 6 insertions(+) >> >> diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >> b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >> index 38561f26837e..f6b9792531a6 100644 >> --- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >> +++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c >> @@ -1954,6 +1954,12 @@ static const struct adreno_info a8xx_gpus[] = { >> }, >> }, >> .preempt_record_size = 19708 * SZ_1K, >> + .speedbins = ADRENO_SPEEDBINS( >> + { 0, 0 }, >> + { 273, 1 }, >> + { 252, 2 }, >> + { 221, 3 }, > > FWIW downstream maps it like this > > 221 -> 0 > 252 -> 1 > 273 -> 2 > default -> 3 > > although it's of course just between the kernel and the DT
Right. It doesn't matter as long as the DT is aligned with this mapping. -Akhil. > > Konrad
