The mmio base address is currently stored in rzg2l_du_device and the devm_platform_ioremap_resource() call lives in rzg2l_du_probe(). In preparation for supporting multiple CRTCs, each with its own register bank, move the mmio pointer and the ioremap call into rzg2l_du_crtc, and update all register accessors in rzg2l_du_crtc.c to use rcrtc->mmio instead of rcdu->mmio.
No functional change intended. Signed-off-by: Tommaso Merciai <[email protected]> --- v6->v7: - New patch. drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c | 23 +++++++++++-------- drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h | 2 ++ drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 5 ---- drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h | 2 -- 4 files changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c index d0f01aa642a7..88915babca12 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.c @@ -67,7 +67,6 @@ static void rzg2l_du_crtc_set_display_timing(struct rzg2l_du_crtc *rcrtc) const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode; unsigned long mode_clock = mode->clock * 1000; u32 ditr0, ditr1, ditr2, ditr3, ditr4, pbcr0; - struct rzg2l_du_device *rcdu = rcrtc->dev; clk_prepare_enable(rcrtc->rzg2l_clocks.dclk); clk_set_rate(rcrtc->rzg2l_clocks.dclk, mode_clock); @@ -90,15 +89,15 @@ static void rzg2l_du_crtc_set_display_timing(struct rzg2l_du_crtc *rcrtc) pbcr0 = DU_PBCR0_PB_DEP(0x1f); - writel(ditr0, rcdu->mmio + DU_DITR0); - writel(ditr1, rcdu->mmio + DU_DITR1); - writel(ditr2, rcdu->mmio + DU_DITR2); - writel(ditr3, rcdu->mmio + DU_DITR3); - writel(ditr4, rcdu->mmio + DU_DITR4); - writel(pbcr0, rcdu->mmio + DU_PBCR0); + writel(ditr0, rcrtc->mmio + DU_DITR0); + writel(ditr1, rcrtc->mmio + DU_DITR1); + writel(ditr2, rcrtc->mmio + DU_DITR2); + writel(ditr3, rcrtc->mmio + DU_DITR3); + writel(ditr4, rcrtc->mmio + DU_DITR4); + writel(pbcr0, rcrtc->mmio + DU_PBCR0); /* Enable auto clear */ - writel(DU_MCR1_PB_AUTOCLR, rcdu->mmio + DU_MCR1); + writel(DU_MCR1_PB_AUTOCLR, rcrtc->mmio + DU_MCR1); } /* ----------------------------------------------------------------------------- @@ -223,7 +222,7 @@ static void rzg2l_du_start_stop(struct rzg2l_du_crtc *rcrtc, bool start) if (start && rzg2l_du_has(rcdu, RZG2L_DU_FEATURE_DPIO_OE)) val |= DU_MCR0_DPI_EN; - writel(start ? val : 0, rcdu->mmio + DU_MCR0); + writel(start ? val : 0, rcrtc->mmio + DU_MCR0); } static void rzg2l_du_crtc_start(struct rzg2l_du_crtc *rcrtc) @@ -380,11 +379,17 @@ static const struct drm_crtc_funcs crtc_funcs_rz = { int rzg2l_du_crtc_create(struct rzg2l_du_device *rcdu) { + struct platform_device *pdev = to_platform_device(rcdu->dev); struct rzg2l_du_crtc *rcrtc = &rcdu->crtcs[0]; struct drm_crtc *crtc = &rcrtc->crtc; struct drm_plane *primary; int ret; + /* I/O resources */ + rcrtc->mmio = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(rcrtc->mmio)) + return PTR_ERR(rcrtc->mmio); + rcrtc->rstc = devm_reset_control_get_optional_shared(rcdu->dev, NULL); if (IS_ERR(rcrtc->rstc)) { dev_err(rcdu->dev, "can't get cpg reset\n"); diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h index cbba38acc377..9b2deb3c589a 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_crtc.h @@ -29,6 +29,7 @@ struct rzg2l_du_format_info; * struct rzg2l_du_crtc - the CRTC, representing a DU superposition processor * @crtc: base DRM CRTC * @dev: the DU device + * @mmio: base address of the DU hardware registers for this CRTC * @initialized: whether the CRTC has been initialized and clocks enabled * @vblank_enable: whether vblank events are enabled on this CRTC * @event: event to post when the pending page flip completes @@ -42,6 +43,7 @@ struct rzg2l_du_crtc { struct drm_crtc crtc; struct rzg2l_du_device *dev; + void __iomem *mmio; bool initialized; bool vblank_enable; diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c index fc55dfffebaf..887b840e63d2 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c @@ -157,11 +157,6 @@ static int rzg2l_du_probe(struct platform_device *pdev) platform_set_drvdata(pdev, rcdu); - /* I/O resources */ - rcdu->mmio = devm_platform_ioremap_resource(pdev, 0); - if (IS_ERR(rcdu->mmio)) - return PTR_ERR(rcdu->mmio); - ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); if (ret) return ret; diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h index baf076d69cda..d0e59b787cd7 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h @@ -66,8 +66,6 @@ struct rzg2l_du_device { struct device *dev; const struct rzg2l_du_device_info *info; - void __iomem *mmio; - struct drm_device ddev; struct rzg2l_du_crtc crtcs[RZG2L_DU_MAX_CRTCS]; -- 2.54.0
