From: Lad Prabhakar <[email protected]> Move pixel clock validation from a fixed encoder check to per SoC constraints stored in rzg2l_du_device_info.
Pixel clock limits differ across SoCs in the RZ DU family and cannot be expressed by a single shared rule. For example, RZ/G2UL (R9A07G043U) limits the DPAD0 pixel clock to 83.5 MHz, while other SoCs such as RZ/T2H require a wider operating range. Add mode_clock_min and mode_clock_max fields to rzg2l_du_device_info to describe the supported pixel clock range for each SoC. Update rzg2l_du_encoder_mode_valid() to return MODE_CLOCK_LOW when the pixel clock falls below mode_clock_min and MODE_CLOCK_HIGH when it exceeds mode_clock_max. Set the pixel clock limits for RZ/G2UL(R9A07G043U) to 20.875MHz minimum and 83.5MHz maximum. Signed-off-by: Lad Prabhakar <[email protected]> --- v1->v2: - Dropped storing info pointer in struct rzg2l_du_encoder as it's not needed. --- drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c | 2 ++ drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h | 4 ++++ drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c | 6 +++++- 3 files changed, 11 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c index 0fef33a5a089..3b7162c6e1f4 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.c @@ -35,6 +35,8 @@ static const struct rzg2l_du_device_info rzg2l_du_r9a07g043u_info = { .port = 0, }, }, + .mode_clock_min = 20875, + .mode_clock_max = 83500, }; static const struct rzg2l_du_device_info rzg2l_du_r9a07g044_info = { diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h index 58806c2a8f2b..885558eb9547 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_drv.h @@ -44,10 +44,14 @@ struct rzg2l_du_output_routing { * struct rzg2l_du_device_info - DU model-specific information * @channels_mask: bit mask of available DU channels * @routes: array of CRTC to output routes, indexed by output (RZG2L_DU_OUTPUT_*) + * @mode_clock_min: minimum pixel clock in kHz + * @mode_clock_max: maximum pixel clock in kHz */ struct rzg2l_du_device_info { unsigned int channels_mask; struct rzg2l_du_output_routing routes[RZG2L_DU_OUTPUT_MAX]; + u32 mode_clock_min; + u32 mode_clock_max; }; #define RZG2L_DU_MAX_CRTCS 1 diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c index 0e567b57a408..5c672549bc84 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_du_encoder.c @@ -50,8 +50,12 @@ rzg2l_du_encoder_mode_valid(struct drm_encoder *encoder, const struct drm_display_mode *mode) { struct rzg2l_du_encoder *renc = to_rzg2l_encoder(encoder); + struct rzg2l_du_device *rcdu = to_rzg2l_du_device(renc->base.dev); + const struct rzg2l_du_device_info *info = rcdu->info; - if (renc->output == RZG2L_DU_OUTPUT_DPAD0 && mode->clock > 83500) + if (info->mode_clock_min && mode->clock < info->mode_clock_min) + return MODE_CLOCK_LOW; + if (info->mode_clock_max && mode->clock > info->mode_clock_max) return MODE_CLOCK_HIGH; return MODE_OK; -- 2.54.0
