On Wed, May 13, 2026 at 03:44:05PM +0800, Damon Ding wrote:
> RK3588 eDP controller requires HCLK_VO1 (video output bus clock)
> to access the VO1 GRF registers and enable the video datapath.
To access GRF? Then it is the same clock input.
AGAIN (reiterated soooo many times by me): you describe here clock
input, NOT OUTPUT.
>
> Previously, the clock was enabled implicitly via the 'rockchip,vo-grf'
> phandle reference, which allowed the eDP to work without explicitly
> managing the hclk_vo1 clock. However, this is not safe or explicit.
>
> Enforce the correct third clock name on a per-compatible basis to
> standardize clock requirements per SoC. This makes the clock
> dependency clear and removes reliance on implicit clock enablement
> from GRF phandle.
>
> Fixes: f855146263b1 ("dt-bindings: display: rockchip: analogix-dp: Add
> support for RK3588")
> Signed-off-by: Damon Ding <[email protected]>
>
> ---
>
> Changes in v4:
> - Modify the commit msg.
>
> Changes in v5:
> - Enforce the correct third clock name on a per-compatible basis.
> - Modify the commit msg simultaneously.
> ---
> .../rockchip/rockchip,analogix-dp.yaml | 37 +++++++++++++++++--
> 1 file changed, 33 insertions(+), 4 deletions(-)
>
> diff --git
> a/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml
>
> b/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml
> index d99b23b88cc5..8001c1facf98 100644
> ---
> a/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml
> +++
> b/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml
> @@ -23,10 +23,7 @@ properties:
>
> clock-names:
> minItems: 2
> - items:
> - - const: dp
> - - const: pclk
> - - const: grf
What is 'grf' clock in such case?
Best regards,
Krzysztof
