From: Jérôme de Bretagne <[email protected]>
Add the vreg_edp_3p3, edp_reg_en and mdss0_dp3 nodes to enable the
Surface Pro 9 5G eDP-based LCD display (LG LP129WT232166).
The enable GPIO 36 was found by decompiling AeoB dumps [1]:
Package ()
{
"CLOCK",
Package ()
{
"gcc_edp3_phy_clkref_en",
0x0000000000000001,
},
},
Package ()
{
"FOOTSWITCH",
Package ()
{
"mdss_0_disp_cc_mdss_core_gdsc",
0x0000000000000001,
0x0000000000000001,
},
},
Package ()
{
"PSTATE_ADJUST",
Package ()
{
0x0000000000000002,
0x0000000000000000,
},
},
Package ()
{
"PSTATE_ADJUST",
Package ()
{
0x0000000000000003,
0x0000000000000001,
},
},
Package ()
{
"PMICVREGVOTE",
Package ()
{
"PPP_RESOURCE_ID_LDO3_B",
0x0000000000000001,
0x0000000000124F80,
0x0000000000000001,
0x0000000000000007,
0x0000000000000000,
"HLOS_DRV",
"REQUIRED",
},
},
Package ()
{
"PMICVREGVOTE",
Package ()
{
"PPP_RESOURCE_ID_LDO6_B",
0x0000000000000001,
0x00000000000D6D80,
0x0000000000000001,
0x0000000000000007,
0x0000000000000000,
"HLOS_DRV",
"REQUIRED",
},
},
Package ()
{
"TLMMGPIO",
Package ()
{
0x0000000000000024, <== GPIO 36
0x0000000000000001,
0x0000000000000000,
0x0000000000000001,
0x0000000000000000,
0x0000000000000000,
},
},
[1]
https://github.com/alexVinarskis/qcom-aeob-dumps/blob/master/microsoft-surface-pro-9-5G-1996/qcdxkmext8280_ARC_part2.json#L156-L168
Signed-off-by: Jérôme de Bretagne <[email protected]>
---
.../boot/dts/qcom/sc8280xp-microsoft-arcata.dts | 64 ++++++++++++++++++++--
1 file changed, 59 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts
b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts
index
14287092fb07ea15e527fd318f7ea2155448b26c..7f1cc1899002529b7ac7340974c99f6ed493d410
100644
--- a/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts
+++ b/arch/arm64/boot/dts/qcom/sc8280xp-microsoft-arcata.dts
@@ -137,6 +137,22 @@ pmic_glink_con1_sbu: endpoint {
};
};
+ vreg_edp_3p3: regulator-edp-3p3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_EDP_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 36 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&edp_reg_en>;
+ pinctrl-names = "default";
+
+ regulator-boot-on;
+ };
+
vreg_edp_bl: regulator-edp-bl {
compatible = "regulator-fixed";
@@ -361,7 +377,6 @@ vreg_l6b: ldo6 {
regulator-max-microvolt = <880000>;
regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
regulator-boot-on;
- regulator-always-on; // FIXME: VDD_A_EDP_0_0P9
};
};
@@ -465,10 +480,6 @@ &dispcc0 {
status = "okay";
};
-&dispcc1 {
- status = "okay";
-};
-
&gpi_dma0 {
status = "okay";
};
@@ -511,6 +522,42 @@ &mdss0_dp1_out {
remote-endpoint = <&usb_1_qmpphy_dp_in>;
};
+&mdss0_dp3 {
+ compatible = "qcom,sc8280xp-edp";
+ /delete-property/ #sound-dai-cells;
+
+ data-lanes = <0 1 2 3>;
+
+ status = "okay";
+
+ aux-bus {
+ panel {
+ compatible = "edp-panel";
+
+ backlight = <&backlight>;
+ power-supply = <&vreg_edp_3p3>;
+
+ port {
+ edp_panel_in: endpoint {
+ remote-endpoint = <&mdss0_dp3_out>;
+ };
+ };
+ };
+ };
+};
+
+&mdss0_dp3_out {
+ remote-endpoint = <&edp_panel_in>;
+};
+
+&mdss0_dp3_phy {
+ compatible = "qcom,sc8280xp-edp-phy";
+ vdda-phy-supply = <&vreg_l6b>;
+ vdda-pll-supply = <&vreg_l3b>;
+
+ status = "okay";
+};
+
&pcie2a {
perst-gpios = <&tlmm 143 GPIO_ACTIVE_LOW>;
wake-gpios = <&tlmm 145 GPIO_ACTIVE_LOW>;
@@ -932,6 +979,13 @@ hstp-sw-ctrl-pins {
};
};
+ edp_reg_en: edp-reg-en-state {
+ pins = "gpio36";
+ function = "gpio";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
nvme_reg_en: nvme-reg-en-state {
pins = "gpio135";
function = "gpio";
--
2.47.3
