From: Sean Paul <[email protected]> Fix a step discontinuity in the Post-CSC Gamma LUT when SDR dimming is active by clamping Segment 2 to the last user-provided LUT entry value instead of hardcoding it to 1.0 (1 << 24).
Link: https://lore.kernel.org/intel-gfx/[email protected]/ #v1 Signed-off-by: Sean Paul <[email protected]> Changes in v2: - Split out into separate patches for pre/post csc fixes - Dropped loop bounds fix in favor of [1] [1]- https://lore.kernel.org/r/[email protected] --- Changes in v2.1: - Rebased on Pranay's patch and sending without in-reply-to drivers/gpu/drm/i915/display/intel_color.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 7ef870cd9a16..7185f3628dcf 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -4038,11 +4038,11 @@ xelpd_program_plane_post_csc_lut(struct intel_dsb *dsb, lut_val); } - /* Segment 2 */ + /* Segment 2 - clamp to the last LUT value to prevent step discontinuity */ do { intel_de_write_dsb(display, dsb, PLANE_POST_CSC_GAMC_DATA_ENH(pipe, plane, 0), - (1 << 24)); + lut_val); } while (i++ < 34); } else { /*TODO: Add for segment 0 */ -- Sean Paul, Software Engineer, Google / Chromium OS
