From: Sean Paul <[email protected]> Fix a typo in the loop condition in xelpd_program_plane_pre_csc_lut for Segment 2 degamma programming, changing 'while (i++ > 130)' to 'while (i++ < 130)'. Also clamp Segment 2 to the last user-provided LUT entry value instead of hardcoding it to 1.0 (1 << 24) to fix a step discontinuity.
Link: https://lore.kernel.org/intel-gfx/[email protected]/ #v1 Signed-off-by: Sean Paul <[email protected]> Changes in v2: - Split out into separate patches for pre/post csc fixes - Dropped loop bounds fix in favor of [1] [1]- https://lore.kernel.org/r/[email protected] --- Changes in v2.1: - Rebased on Pranay's patch and sending without in-reply-to drivers/gpu/drm/i915/display/intel_color.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 7185f3628dcf..458508bcf1f4 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -3968,6 +3968,7 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb, enum plane_id plane = to_intel_plane(state->plane)->id; const struct drm_color_lut32 *pre_csc_lut = plane_state->hw.degamma_lut->data; u32 i, lut_size; + u32 lut_val = 1 << 24; if (icl_is_hdr_plane(display, plane)) { lut_size = 128; @@ -3978,7 +3979,7 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb, if (pre_csc_lut) { for (i = 0; i < lut_size; i++) { - u32 lut_val = drm_color_lut32_extract(pre_csc_lut[i].green, 24); + lut_val = drm_color_lut32_extract(pre_csc_lut[i].green, 24); intel_de_write_dsb(display, dsb, PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), @@ -3990,7 +3991,7 @@ xelpd_program_plane_pre_csc_lut(struct intel_dsb *dsb, do { intel_de_write_dsb(display, dsb, PLANE_PRE_CSC_GAMC_DATA_ENH(pipe, plane, 0), - (1 << 24)); + lut_val); } while (i++ < 130); } else { for (i = 0; i < lut_size; i++) { -- Sean Paul, Software Engineer, Google / Chromium OS
