All published NPU firmware versions support D0i3 delayed entry flow, making this workaround obsolete. It was originally added as a safety measure for potential firmware bugs.
Recent firmware dropped legacy D0i3 entry support, so the workaround can't be used anyway. Hardcode d0i3_delayed_entry boot param to 1 to ensure older firmware works in the correct mode. No functional changes, just dead code cleanup. Signed-off-by: Andrzej Kacprowski <[email protected]> --- drivers/accel/ivpu/ivpu_drv.h | 3 --- drivers/accel/ivpu/ivpu_fw.c | 23 ++--------------------- drivers/accel/ivpu/ivpu_jsm_msg.c | 3 --- drivers/accel/ivpu/vpu_boot_api.h | 6 ++++-- 4 files changed, 6 insertions(+), 29 deletions(-) diff --git a/drivers/accel/ivpu/ivpu_drv.h b/drivers/accel/ivpu/ivpu_drv.h index c77dde310e81..9eefbbb7ba11 100644 --- a/drivers/accel/ivpu/ivpu_drv.h +++ b/drivers/accel/ivpu/ivpu_drv.h @@ -111,7 +111,6 @@ struct ivpu_wa_table { bool clear_runtime_mem; bool interrupt_clear_with_0; bool disable_clock_relinquish; - bool disable_d0i3_msg; bool wp0_during_power_up; bool disable_d0i2; }; @@ -220,8 +219,6 @@ extern bool ivpu_force_snoop; #define IVPU_TEST_MODE_FW_TEST BIT(0) #define IVPU_TEST_MODE_NULL_HW BIT(1) #define IVPU_TEST_MODE_NULL_SUBMISSION BIT(2) -#define IVPU_TEST_MODE_D0I3_MSG_DISABLE BIT(4) -#define IVPU_TEST_MODE_D0I3_MSG_ENABLE BIT(5) #define IVPU_TEST_MODE_MIP_DISABLE BIT(6) #define IVPU_TEST_MODE_DISABLE_TIMEOUTS BIT(8) #define IVPU_TEST_MODE_TURBO_ENABLE BIT(9) diff --git a/drivers/accel/ivpu/ivpu_fw.c b/drivers/accel/ivpu/ivpu_fw.c index 107f8ad31050..7db199e04f7c 100644 --- a/drivers/accel/ivpu/ivpu_fw.c +++ b/drivers/accel/ivpu/ivpu_fw.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0-only /* - * Copyright (C) 2020-2025 Intel Corporation + * Copyright (C) 2020-2026 Intel Corporation */ #include <linux/firmware.h> @@ -347,22 +347,6 @@ static void ivpu_fw_release(struct ivpu_device *vdev) release_firmware(vdev->fw->file); } -/* Initialize workarounds that depend on FW version */ -static void -ivpu_fw_init_wa(struct ivpu_device *vdev) -{ - const struct vpu_firmware_header *fw_hdr = (const void *)vdev->fw->file->data; - - if (IVPU_FW_CHECK_API_VER_LT(vdev, fw_hdr, BOOT, 3, 17) || - (ivpu_test_mode & IVPU_TEST_MODE_D0I3_MSG_DISABLE)) - vdev->wa.disable_d0i3_msg = true; - - /* Force enable the feature for testing purposes */ - if (ivpu_test_mode & IVPU_TEST_MODE_D0I3_MSG_ENABLE) - vdev->wa.disable_d0i3_msg = false; - - IVPU_PRINT_WA(disable_d0i3_msg); -} static int ivpu_fw_mem_init(struct ivpu_device *vdev) { @@ -480,8 +464,6 @@ int ivpu_fw_init(struct ivpu_device *vdev) if (ret) goto err_fw_release; - ivpu_fw_init_wa(vdev); - ret = ivpu_fw_mem_init(vdev); if (ret) goto err_fw_release; @@ -711,8 +693,7 @@ void ivpu_fw_boot_params_setup(struct ivpu_device *vdev, struct vpu_boot_params if (vdev->fw->sched_mode == VPU_SCHEDULING_MODE_HW) boot_params->vpu_focus_present_timer_ms = IVPU_FOCUS_PRESENT_TIMER_MS; boot_params->dvfs_mode = vdev->fw->dvfs_mode; - if (!IVPU_WA(disable_d0i3_msg)) - boot_params->d0i3_delayed_entry = 1; + boot_params->d0i3_delayed_entry = 1; boot_params->d0i3_residency_time_us = 0; boot_params->d0i3_entry_vpu_ts = 0; if (IVPU_WA(disable_d0i2)) diff --git a/drivers/accel/ivpu/ivpu_jsm_msg.c b/drivers/accel/ivpu/ivpu_jsm_msg.c index 17b42a76aef9..6361fe50596e 100644 --- a/drivers/accel/ivpu/ivpu_jsm_msg.c +++ b/drivers/accel/ivpu/ivpu_jsm_msg.c @@ -275,9 +275,6 @@ int ivpu_jsm_pwr_d0i3_enter(struct ivpu_device *vdev) struct vpu_jsm_msg resp; int ret; - if (IVPU_WA(disable_d0i3_msg)) - return 0; - req.payload.pwr_d0i3_enter.send_response = 1; ret = ivpu_ipc_send_receive_internal(vdev, &req, VPU_JSM_MSG_PWR_D0I3_ENTER_DONE, &resp, diff --git a/drivers/accel/ivpu/vpu_boot_api.h b/drivers/accel/ivpu/vpu_boot_api.h index a41170bbc6b7..06c092d5e675 100644 --- a/drivers/accel/ivpu/vpu_boot_api.h +++ b/drivers/accel/ivpu/vpu_boot_api.h @@ -41,7 +41,7 @@ /** * API header changed (field names, documentation, formatting) but API itself has not been changed */ -#define VPU_BOOT_API_VER_PATCH 4 +#define VPU_BOOT_API_VER_PATCH 5 /** * Index in the API version table @@ -320,9 +320,11 @@ struct vpu_boot_params { u64 dvfs_param; /** * D0i3 delayed entry - * Bit0: Disable CPU state save on D0i2 entry flow. + * Bit 0: Disable CPU state save on D0i2 entry flow. * 0: Every D0i2 entry saves state. Save state IPC message ignored. * 1: IPC message required to save state on D0i3 entry flow. + * NOTE: This parameter is deprecated starting NPU50xx+. Bit 0 is now hardcoded to 1, + * meaning CPU state save always requires IPC message on D0i3 entry flow. */ u32 d0i3_delayed_entry; /** Time spent by VPU in D0i3 state */ -- 2.43.0
