From: Antonin Malzieu Ridolfi <[email protected]> Move PFSP register definition into falcon module and update registers visibility.
Signed-off-by: Antonin Malzieu Ridolfi <[email protected]> --- drivers/gpu/nova-core/falcon/fsp.rs | 14 +++++++------- drivers/gpu/nova-core/falcon/regs.rs | 21 +++++++++++++++++++++ drivers/gpu/nova-core/regs.rs | 21 --------------------- 3 files changed, 28 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/nova-core/falcon/fsp.rs b/drivers/gpu/nova-core/falcon/fsp.rs index 52cdb84ef0e8..547843e6483c 100644 --- a/drivers/gpu/nova-core/falcon/fsp.rs +++ b/drivers/gpu/nova-core/falcon/fsp.rs @@ -26,10 +26,10 @@ Falcon, FalconEngine, PFalcon2Base, - PFalconBase, // + PFalconBase, + regs, // }, - num, - regs, // + num, // }; /// FSP message timeout in milliseconds. @@ -61,7 +61,7 @@ fn write_emem(&mut self, bar: Bar0<'_>, data: &[u8]) -> Result { // Begin a write burst at offset `0`, auto-incrementing on each write. bar.write( WithBase::of::<Fsp>(), - regs::NV_PFALCON_FALCON_EMEMC::zeroed().with_aincw(true), + crate::regs::NV_PFALCON_FALCON_EMEMC::zeroed().with_aincw(true), ); for chunk in data.chunks_exact(4) { @@ -70,7 +70,7 @@ fn write_emem(&mut self, bar: Bar0<'_>, data: &[u8]) -> Result { // Write the next 32-bit `value`; hardware advances the offset. bar.write( WithBase::of::<Fsp>(), - regs::NV_PFALCON_FALCON_EMEMD::zeroed().with_data(value), + crate::regs::NV_PFALCON_FALCON_EMEMD::zeroed().with_data(value), ); } @@ -89,12 +89,12 @@ fn read_emem(&mut self, bar: Bar0<'_>, data: &mut [u8]) -> Result { // Begin a read burst at offset `0`, auto-incrementing on each read. bar.write( WithBase::of::<Fsp>(), - regs::NV_PFALCON_FALCON_EMEMC::zeroed().with_aincr(true), + crate::regs::NV_PFALCON_FALCON_EMEMC::zeroed().with_aincr(true), ); for chunk in data.chunks_exact_mut(4) { // Read the next 32-bit word; hardware advances the offset. - let value = bar.read(regs::NV_PFALCON_FALCON_EMEMD::of::<Fsp>()).data(); + let value = bar.read(crate::regs::NV_PFALCON_FALCON_EMEMD::of::<Fsp>()).data(); chunk.copy_from_slice(&value.to_le_bytes()); } diff --git a/drivers/gpu/nova-core/falcon/regs.rs b/drivers/gpu/nova-core/falcon/regs.rs index 4d4e69b235fc..81530abfb54c 100644 --- a/drivers/gpu/nova-core/falcon/regs.rs +++ b/drivers/gpu/nova-core/falcon/regs.rs @@ -53,3 +53,24 @@ 0:0 valid => bool; } } + +// FSP (Foundation Security Processor) queue registers for Hopper/Blackwell Chain of Trust. +// These registers manage falcon EMEM communication queues. + +register! { + pub(super) NV_PFSP_QUEUE_HEAD(u32)[8] @ 0x008f2c00 { + 31:0 address => u32; + } + + pub(super) NV_PFSP_QUEUE_TAIL(u32)[8] @ 0x008f2c04 { + 31:0 address => u32; + } + + pub(super) NV_PFSP_MSGQ_HEAD(u32)[8] @ 0x008f2c80 { + 31:0 val => u32; + } + + pub(super) NV_PFSP_MSGQ_TAIL(u32)[8] @ 0x008f2c84 { + 31:0 val => u32; + } +} diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index b21a5adc723a..9069aeff1ee4 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -491,27 +491,6 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { } } -// FSP (Foundation Security Processor) queue registers for Hopper/Blackwell Chain of Trust. -// These registers manage falcon EMEM communication queues. - -register! { - pub(crate) NV_PFSP_QUEUE_HEAD(u32)[8] @ 0x008f2c00 { - 31:0 address => u32; - } - - pub(crate) NV_PFSP_QUEUE_TAIL(u32)[8] @ 0x008f2c04 { - 31:0 address => u32; - } - - pub(crate) NV_PFSP_MSGQ_HEAD(u32)[8] @ 0x008f2c80 { - 31:0 val => u32; - } - - pub(crate) NV_PFSP_MSGQ_TAIL(u32)[8] @ 0x008f2c84 { - 31:0 val => u32; - } -} - // The modules below provide registers that are not identical on all supported chips. They should // only be used in HAL modules. -- 2.54.0
