Thank you for your contribution! Sashiko AI review found 2 potential issue(s) to consider: - [High] The `clocks` node is incorrectly assigned to `DOMAIN_VPLL` instead of `DOMAIN_VAPE` and includes an unresolved `CHECKME` comment. - [Medium] Adding `power-domains` to nodes whose binding schemas do not allow it will cause `dtbs_check` validation errors. --
commit 57cdb12b349af07637860b10a8f8232b9e2930bc Author: Linus Walleij <[email protected]> ARM: dts: ux500: Add power domains Add the actual power domains to all the SoC peripherals. > diff --git a/arch/arm/boot/dts/st/ste-dbx5x0.dtsi > b/arch/arm/boot/dts/st/ste-dbx5x0.dtsi > index d76a65da70111..a6fef302c994e 100644 > --- a/arch/arm/boot/dts/st/ste-dbx5x0.dtsi > +++ b/arch/arm/boot/dts/st/ste-dbx5x0.dtsi [ ... ] > @@ -334,6 +340,7 @@ L2: cache-controller { > compatible = "arm,pl310-cache"; > reg = <0xa0412000 0x1000>; > interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; > + power-domains = <&pm_domains DOMAIN_VARM>; [Severity: Medium] Will adding power-domains here cause dtbs_check validation errors? The l2c2x0.yaml binding schema (along with others modified in this patch like arm/pmu.yaml, stericsson,u8500-clks.yaml, arm,twd-timer.yaml, arm,twd-wdt.yaml, and ste,mcde.yaml) does not include power-domains in its list of allowed properties. Do these bindings need to be updated to document the power-domains capability before it can be used? > cache-unified; > cache-level = <2>; > }; [ ... ] > @@ -357,6 +365,7 @@ clocks { > reg = <0x8012f000 0x1000>, <0x8011f000 0x1000>, > <0x8000f000 0x1000>, <0xa03ff000 0x1000>, > <0xa03cf000 0x1000>; > + power-domains = <&pm_domains DOMAIN_VPLL>; /* CHECKME: > correct domain? */ [Severity: High] Should this be DOMAIN_VAPE instead of DOMAIN_VPLL? The PRCC registers mapped here for peripheral groups 1, 2, 3, 5, and 6 reside in the VAPE power domain alongside the peripherals they clock. If the clock controller is assigned to DOMAIN_VPLL, the power domain framework won't guarantee DOMAIN_VAPE is powered on when accessing these registers, which could cause a synchronous external abort. Also, is the CHECKME comment intended to be resolved before merging? -- Sashiko AI review ยท https://sashiko.dev/#/patchset/[email protected]?part=5
