Add documentation for the extended DMA Engine (exDMA) IP found in the newer generation SoCs like MT8196, MT8894, MT6991, and their variants.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]> --- .../mediatek/mediatek,mt8196-exdma.yaml | 104 ++++++++++++++++++ 1 file changed, 104 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-exdma.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-exdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-exdma.yaml new file mode 100644 index 000000000000..ca08a74ef7ad --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-exdma.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8196-exdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Display Overlay extended DMA (exDMA) Engine + +maintainers: + - AngeloGioacchino Del Regno <[email protected]> + +description: + The MediaTek Display Overlay extended DMA (exDMA) Engine hardware is used + to configure the Display Controller to read the data from DRAM to perform + layer overlaying. + This hardware also includes color conversion functions to output pixels + processed into a consistent color domain. + +properties: + compatible: + - const: mediatek,mt8196-disp-exdma + + reg: + maxItems: 1 + + "#dma-cells": + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + + port@1: + $ref: /schemas/graph.yaml#/properties/port + + required: + - port@0 + - port@1 + + trigger-sources: + maxItems: 1 + +required: + - compatible + - reg + - "#dma-cells" + - clocks + - clock-names + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/mediatek,mt8196-clock.h> + #include <dt-bindings/power/mediatek,mt8196-power.h> + + dma-controller@32850000 { + compatible = "mediatek,mt8196-disp-exdma"; + reg = <0x32850000 0x1000>; + #dma-cells = <1>; + clocks = <&ovlsys0 CLK_OVL_EXDMA2>; + power-domains = <&hpm_hwv MT8196_POWER_DOMAIN_OVL0_DORMANT>; + trigger-sources = <&ovl0_mutex 2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_resizer0_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + endpoint@0 { + reg = <0>; + remote-endpoint = <&blender0_1_in>; + }; + }; + }; + }; + +... -- 2.54.0
