Add documentation for the Overlay Output Processor IP found in the newer Generation SoCs like MT8196, MT8894, MT6991, and their variants.
Signed-off-by: AngeloGioacchino Del Regno <[email protected]> --- .../mediatek/mediatek,mt8196-outproc.yaml | 107 ++++++++++++++++++ 1 file changed, 107 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-outproc.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-outproc.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-outproc.yaml new file mode 100644 index 000000000000..634107db269c --- /dev/null +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,mt8196-outproc.yaml @@ -0,0 +1,107 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mediatek/mediatek,mt8196-outproc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Display Overlay Output Processor + +maintainers: + - AngeloGioacchino Del Regno <[email protected]> + +description: + The MediaTek Display Overlay Output Processor hardware handles the + post-stage of pixel processing in the layer overlaying process and + is also capable of performing gamma correction, ensuring that the + per-pixel values are within the expected luma range. + If an instance of this hardware is configured as last stage, it is + also capable of generating VBlank (Frame Done) events which can be + then dispatched either via an interrupt (to the CPU) or through a + Global Command Engine (GCE) Event, internally sent to programmable + Command Queue (CMDQ) Engine(s) for offloading purposes. + +properties: + compatible: + - const: mediatek,mt8196-disp-outproc + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + description: Optional VBlank event interrupt + maxItems: 1 + + power-domains: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + + port@1: + $ref: /schemas/graph.yaml#/properties/port + + required: + - port@0 + - port@1 + + trigger-sources: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/mediatek,mt8196-clock.h> + #include <dt-bindings/power/mediatek,mt8196-power.h> + + outproc@32970000 { + compatible = "mediatek,mt8196-disp-outproc"; + reg = <0x32970000 0x1000>; + clocks = <&ovlsys0 CLK_OVL_OUTPROC0>; + power-domains = <&hpm_hwv MT8196_POWER_DOMAIN_OVL0_DORMANT>; + trigger-sources = <&ovl0_mutex 20>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + endpoint@0 { + reg = <0>; + remote-endpoint = <&blender0_8_out>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + endpoint@0 { + reg = <0>; + remote-endpoint = <&ovl0_directlink_out_relay6>; + }; + }; + }; + }; + +... -- 2.54.0
