Add the LVDS transmitter node. It has no register block of its own - it is programmed through the GRF and borrows the MIPI DSI0 D-PHY - so it carries no reg, only the DSITX_0 pclk, the phy and the VO power domain.
Disabled by default; boards that route LVDS enable it along with dsi_dphy0 and wire lvds_in to a VOP2 video port. Signed-off-by: Rok Markovic <[email protected]> Assisted-by: Claude:claude-opus-4-8 --- arch/arm64/boot/dts/rockchip/rk356x-base.dtsi | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi index 64bdd8b..9244b55 100644 --- a/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk356x-base.dtsi @@ -878,6 +878,31 @@ }; }; + lvds: lvds { + compatible = "rockchip,rk3568-lvds"; + clocks = <&cru PCLK_DSITX_0>; + clock-names = "pclk_lvds"; + phys = <&dsi_dphy0>; + phy-names = "dphy"; + power-domains = <&power RK3568_PD_VO>; + rockchip,grf = <&grf>; + rockchip,output = "lvds"; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + lvds_in: port@0 { + reg = <0>; + }; + + lvds_out: port@1 { + reg = <1>; + }; + }; + }; + qos_gpu: qos@fe128000 { compatible = "rockchip,rk3568-qos", "syscon"; reg = <0x0 0xfe128000 0x0 0x20>; -- 2.43.0
