On Mon, Jul 20, 2026 at 04:43:54PM +0800, Yongxing Mou wrote:
> Kaanapali (SM8750) and Glymur use two display power domains.
> CORE_GDSC powers the main display hardware while INT2_GDSC powers
> a subset of SSPP blocks (VIG2/VIG3/DMA5/DMA6).
>
> The MDSS driver currently relies on the default runtime PM handling
> and does not enable the secondary INT2_GDSC. As a result, display
> pipes backed by INT2_GDSC remain inaccessible.
>
> Attach and manage both power domains explicitly and enable them
> during MDSS runtime PM activation.
>
> Signed-off-by: Yongxing Mou <[email protected]>
> ---
> drivers/gpu/drm/msm/msm_mdss.c | 53
> +++++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 52 insertions(+), 1 deletion(-)
Why is it being handled in the MDSS rather than DPU?
> @@ -421,6 +451,27 @@ static struct msm_mdss *msm_mdss_init(struct
> platform_device *pdev, bool is_mdp5
> irq_set_chained_handler_and_data(irq, msm_mdss_irq,
> msm_mdss);
>
> + /*
> + * When two power domains are listed in DT, the core framework does not
> + * auto-attach either of them. Attach and manage both explicitly so
> + * that INT2_GDSC (needed for VIG2/VIG3) is enabled alongside the main
> + * CORE_GDSC. Single-domain platforms are unaffected.
> + */
> + if (of_count_phandle_with_args(pdev->dev.of_node, "power-domains",
> + "#power-domain-cells") > 1) {
> + static const char * const mdss_pd_names[] = { "core", "int2" };
> + static const struct dev_pm_domain_attach_data pd_data = {
> + .pd_names = mdss_pd_names,
> + .num_pd_names = ARRAY_SIZE(mdss_pd_names),
> + .pd_flags = PD_FLAG_NO_DEV_LINK,
Can't you use DL_FLAG_PM_RUNTIME here?
> + };
> +
> + ret = devm_pm_domain_attach_list(&pdev->dev, &pd_data,
> + &msm_mdss->pd_list);
> + if (ret < 0)
> + return ERR_PTR(ret);
> + }
> +
> pm_runtime_enable(&pdev->dev);
>
> return msm_mdss;
>
> --
> 2.43.0
>
--
With best wishes
Dmitry
