On Thu, Jul 30, 2026 at 07:36:41PM +0200, Leander Kieweg wrote:
> Add Device Tree binding documentation for GlandaGPU, a custom
> FPGA-based 2D display controller.
>
> For hardware designs and RTL sources, see:
> https://github.com/stiangglanda/GlandaGPU
>
> Signed-off-by: Leander Kieweg <[email protected]>
> ---
> .../bindings/display/glanda,gpu.yaml | 55 +++++++++++++++++++
> .../devicetree/bindings/vendor-prefixes.yaml | 2 +
> 2 files changed, 57 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/glanda,gpu.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/glanda,gpu.yaml
> b/Documentation/devicetree/bindings/display/glanda,gpu.yaml
> new file mode 100644
> index 000000000..988a30946
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/glanda,gpu.yaml
> @@ -0,0 +1,55 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/glanda,gpu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: GlandaGPU 2D Hardware Accelerated Display Controller
> +
> +maintainers:
> + - Leander Kieweg <[email protected]>
> +
> +description: |
> + GlandaGPU is a custom FPGA soft-IP core providing a simple
> + 2D hardware-accelerated drawing engine with a VGA-compatible
> + display output. The register window covers a combined VRAM + MMIO
> + region, with MMIO registers at a fixed offset within it.
> +
> + For hardware designs and RTL sources, see:
> + https://github.com/stiangglanda/GlandaGPU
> +
> +properties:
> + compatible:
> + const: glanda,gpu-1.0
What does this 1.0 correspond to? There is no such tag on linked Github.
> +
> + reg:
> + maxItems: 1
> + description:
> + Combined VRAM + MMIO register window (VRAM at offset 0,
> + MMIO registers at offset 0x00200000 within this range).
> +
> + interrupts:
> + maxItems: 1
> +
> + clocks:
> + maxItems: 1
> + description: Bus and pixel clock provided to the FPGA IP.
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> + gpu@c0000000 {
> + compatible = "glanda,gpu-1.0";
> + reg = <0xc0000000 0x1000000>;
> + interrupt-parent = <&intc>;
> + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&osc1>;
> + };
> diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> index b1af9deac..b8b7a5401 100644
> --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
> +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
> @@ -666,6 +666,8 @@ patternProperties:
> description: Giantplus Technology Co., Ltd.
> "^gira,.*":
> description: Gira Giersiepen GmbH & Co. KG
> + "^glanda,.*":
> + description: GlandaGPU
Vendor prefixes are per actual vendor, not product.
I have doubts this is needed in the first place. As a pure FPGA design,
this cannot work alone and you cannot get it alone (at least yet,
happily to see resources proving me wrong). Thus it will be always
customized per final board design, thus that final compatible is what
matters.
Best regards,
Krzysztof
