From: Suraj Kandpal <[email protected]> Add HDMI FRL Tables for LT PHY i.e for the rates of 3G, 6G, 8G, 10G and 12G.
Bspec: 74667 Signed-off-by: Suraj Kandpal <[email protected]> --- drivers/gpu/drm/i915/display/intel_lt_phy.c | 270 ++++++++++++++++++++ 1 file changed, 270 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c index 8fc6d230493f..a16401e42ed9 100644 --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c @@ -950,11 +950,281 @@ static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_5p94 = { }, }; +static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_3g0 = { + .config = { + 0x85, + 0x2d, + 0x0, + }, + .addr_msb = { + 0x87, + 0x87, + 0x87, + 0x87, + 0x88, + 0x88, + 0x88, + 0x88, + 0x88, + 0x88, + 0x88, + 0x88, + 0x88, + }, + .addr_lsb = { + 0x10, + 0x0c, + 0x14, + 0xe4, + 0x0c, + 0x10, + 0x14, + 0x18, + 0x48, + 0x40, + 0x4c, + 0x24, + 0x44, + }, + .data = { + { 0x0, 0x4c, 0x2, 0x0 }, + { 0x5, 0xa, 0x27, 0x0 }, + { 0x80, 0x0, 0x0, 0x0 }, + { 0x4, 0x9, 0x1, 0x28 }, + { 0xf2, 0x2e, 0x83, 0x10 }, + { 0x80, 0x0f, 0xf9, 0x53 }, + { 0x84, 0x24, 0x0, 0x0 }, + { 0x0, 0xe0, 0x1, 0x0 }, + { 0x4b, 0x48, 0x0, 0x0 }, + { 0x27, 0x8, 0x0, 0x0 }, + { 0x5a, 0x13, 0x29, 0x13 }, + { 0x0, 0x40, 0xa0, 0x0 }, + { 0x0, 0x0, 0x0, 0x0 }, + }, +}; + +static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_6g0 = { + .config = { + 0x8d, + 0x2d, + 0x0, + }, + .addr_msb = { + 0x87, + 0x87, + 0x87, + 0x87, + 0x88, + 0x88, + 0x88, + 0x88, + 0x88, + 0x88, + 0x88, + 0x88, + 0x88, + }, + .addr_lsb = { + 0x10, + 0x0c, + 0x14, + 0xe4, + 0x0c, + 0x10, + 0x14, + 0x18, + 0x48, + 0x40, + 0x4c, + 0x24, + 0x44, + }, + .data = { + { 0x0, 0x4c, 0x2, 0x0 }, + { 0x2, 0x8a, 0x27, 0x0 }, + { 0x80, 0x0, 0x0, 0x0 }, + { 0x4, 0x4, 0x80, 0xa8 }, + { 0xf2, 0x2e, 0x83, 0x10 }, + { 0x80, 0x0f, 0xf9, 0x53 }, + { 0x84, 0x24, 0x0, 0x0 }, + { 0x0, 0xe0, 0x1, 0x0 }, + { 0x4b, 0x48, 0x0, 0x0 }, + { 0x27, 0x8, 0x0, 0x0 }, + { 0x5a, 0x13, 0x29, 0x13 }, + { 0x0, 0x40, 0xa0, 0x0 }, + { 0x0, 0x0, 0x0, 0x0 }, + }, +}; + +static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_8g0 = { + .config = { + 0x95, + 0x2d, + 0x0, + }, + .addr_msb = { + 0x87, + 0x87, + 0x87, + 0x87, + 0x88, + 0x88, + 0x88, + 0x88, + 0x88, + 0x88, + 0x88, + 0x88, + 0x88, + }, + .addr_lsb = { + 0x10, + 0x0c, + 0x14, + 0xe4, + 0x0c, + 0x10, + 0x14, + 0x18, + 0x48, + 0x40, + 0x4c, + 0x24, + 0x44, + }, + .data = { + { 0x0, 0x4c, 0x2, 0x0 }, + { 0x2, 0x8a, 0x34, 0x0 }, + { 0xaa, 0xaa, 0xaa, 0xaa }, + { 0x5, 0x4, 0x80, 0xa8 }, + { 0xf2, 0x22, 0x83, 0x10 }, + { 0x80, 0x0f, 0xf9, 0xb5 }, + { 0x84, 0x24, 0x0, 0x0 }, + { 0x0, 0xe0, 0x1, 0x0 }, + { 0x4b, 0x48, 0x0, 0x0 }, + { 0x27, 0x8, 0x0, 0x0 }, + { 0x5a, 0x13, 0x29, 0x13 }, + { 0x0, 0x40, 0xa0, 0x0 }, + { 0x0, 0x0, 0x0, 0x0 }, + }, +}; + +static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_10g0 = { + .config = { + 0x1d, + 0x2d, + 0x0, + }, + .addr_msb = { + 0x85, + 0x85, + 0x85, + 0x85, + 0x86, + 0x86, + 0x86, + 0x86, + 0x86, + 0x00, + 0x86, + 0x86, + 0x86, + }, + .addr_lsb = { + 0x10, + 0x0c, + 0x14, + 0xe4, + 0x0c, + 0x10, + 0x14, + 0x18, + 0x48, + 0x00, + 0x4c, + 0x24, + 0x44, + }, + .data = { + { 0x0, 0x4c, 0x2, 0x0 }, + { 0x1, 0x49, 0x20, 0x80 }, + { 0x6a, 0xaa, 0xaa, 0xab }, + { 0x0, 0x6, 0x4, 0x94 }, + { 0xfa, 0x1c, 0x83, 0x11 }, + { 0x80, 0x0f, 0xf9, 0x53 }, + { 0x84, 0x26, 0x4, 0x4 }, + { 0x0, 0xe0, 0x1, 0x0 }, + { 0x45, 0x48, 0x0, 0x0 }, + { 0x27, 0x8, 0x0, 0x0 }, + { 0x5a, 0x14, 0x2a, 0x14 }, + { 0x0, 0x5b, 0xe0, 0x8 }, + { 0x0, 0x0, 0x0, 0x0 }, + }, +}; + +static const struct intel_lt_phy_pll_state xe3plpd_lt_hdmi_12g0 = { + .config = { + 0xa5, + 0x2d, + 0x0, + }, + .addr_msb = { + 0x87, + 0x87, + 0x87, + 0x87, + 0x88, + 0x88, + 0x88, + 0x88, + 0x88, + 0x88, + 0x88, + 0x88, + 0x88, + }, + .addr_lsb = { + 0x10, + 0x0c, + 0x14, + 0xe4, + 0x0c, + 0x10, + 0x14, + 0x18, + 0x48, + 0x40, + 0x4c, + 0x24, + 0x44, + }, + .data = { + { 0x0, 0x4c, 0x2, 0x0 }, + { 0x1, 0x49, 0x27, 0x0 }, + { 0x80, 0x0, 0x0, 0x0 }, + { 0x8, 0x4, 0x80, 0xb2 }, + { 0xf2, 0x2e, 0x83, 0x10 }, + { 0x80, 0x0f, 0xf9, 0x53 }, + { 0x84, 0x24, 0x0, 0x0 }, + { 0x0, 0xe0, 0x1, 0x0 }, + { 0x4b, 0x48, 0x0, 0x0 }, + { 0x27, 0x8, 0x0, 0x0 }, + { 0x5a, 0x14, 0x29, 0x14 }, + { 0x0, 0x40, 0xa0, 0x0 }, + { 0x0, 0x0, 0x0, 0x0 }, + }, +}; + static const struct intel_lt_phy_pll_params xe3plpd_lt_hdmi_tables[] = { LT_PHY_PLL_HDMI_PARAMS(25200, xe3plpd_lt_hdmi_252), LT_PHY_PLL_HDMI_PARAMS(74250, xe3plpd_lt_hdmi_742p5), LT_PHY_PLL_HDMI_PARAMS(148500, xe3plpd_lt_hdmi_1p485), LT_PHY_PLL_HDMI_PARAMS(594000, xe3plpd_lt_hdmi_5p94), + LT_PHY_PLL_HDMI_PARAMS(300000, xe3plpd_lt_hdmi_3g0), + LT_PHY_PLL_HDMI_PARAMS(600000, xe3plpd_lt_hdmi_6g0), + LT_PHY_PLL_HDMI_PARAMS(800000, xe3plpd_lt_hdmi_8g0), + LT_PHY_PLL_HDMI_PARAMS(1000000, xe3plpd_lt_hdmi_10g0), + LT_PHY_PLL_HDMI_PARAMS(1200000, xe3plpd_lt_hdmi_12g0), {} }; -- 2.50.1
