Introduce helper intel_lt_phy_hdmi_frl_rate_valid() to check if the given FRL rate is supported for the LT Phy.
Signed-off-by: Ankit Nautiyal <[email protected]> --- drivers/gpu/drm/i915/display/intel_lt_phy.c | 16 ++++++++++++++++ drivers/gpu/drm/i915/display/intel_lt_phy.h | 1 + 2 files changed, 17 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c b/drivers/gpu/drm/i915/display/intel_lt_phy.c index 2c1da689fe00..f7265d32915d 100644 --- a/drivers/gpu/drm/i915/display/intel_lt_phy.c +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c @@ -2652,3 +2652,19 @@ void intel_lt_phy_verify_plls(struct intel_display *display) intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_edp_tables); intel_lt_phy_pll_verify_tables(display, xe3plpd_lt_hdmi_tables); } + +enum drm_mode_status intel_lt_phy_hdmi_frl_rate_valid(int clock_rate) +{ + const struct intel_lt_phy_pll_params *tables = xe3plpd_lt_hdmi_tables; + int i; + + for (i = 0; tables[i].name; i++) { + if (!intel_hdmi_is_frl(tables[i].clock_rate)) + continue; + + if (clock_rate == tables[i].clock_rate) + return MODE_OK; + } + + return MODE_CLOCK_RANGE; +} diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.h b/drivers/gpu/drm/i915/display/intel_lt_phy.h index 16de39484779..20714ecd9f62 100644 --- a/drivers/gpu/drm/i915/display/intel_lt_phy.h +++ b/drivers/gpu/drm/i915/display/intel_lt_phy.h @@ -49,5 +49,6 @@ void intel_xe3plpd_pll_enable(struct intel_encoder *encoder, const struct intel_dpll_hw_state *dpll_hw_state); void intel_xe3plpd_pll_disable(struct intel_encoder *encoder); void intel_lt_phy_verify_plls(struct intel_display *display); +enum drm_mode_status intel_lt_phy_hdmi_frl_rate_valid(int clock_rate); #endif /* __INTEL_LT_PHY_H__ */ -- 2.50.1
