Introduce helpers to write FRL CFG refister bits.
Signed-off-by: Ankit Nautiyal <[email protected]>
---
drivers/gpu/drm/i915/display/intel_hdmi.c | 16 ++++++++++++++++
drivers/gpu/drm/i915/display/intel_hdmi.h | 1 +
2 files changed, 17 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c
b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 7170546f4779..4d547c27914c 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3992,3 +3992,19 @@ void intel_hdmi_disable_frl(struct intel_encoder
*encoder,
intel_hdmi_reset_frl_config(intel_hdmi);
}
+
+void intel_hdmi_frl_cfg_write(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_trans = crtc_state->cpu_transcoder;
+ u32 val;
+
+ if (!crtc_state->frl.enable)
+ return;
+
+ val = TRANS_HDMI_R_B_SCHED_ENABLE(crtc_state->frl.rsrc_sched_en);
+ val |=
TRANS_HDMI_ACTIVE_CHAR_BUF_THRESH(crtc_state->frl.active_char_buf_threshold);
+ val |= TRANS_HDMI_MIN_BLANK_CHAR(TRANS_HDMI_MIN_BLANK_CHAR_VAL);
+
+ intel_de_rmw(display, TRANS_HDMI_FRL_CFG(display, cpu_trans), 0, val);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h
b/drivers/gpu/drm/i915/display/intel_hdmi.h
index 0e78e700ebf9..41d0a850ec76 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -82,6 +82,7 @@ void intel_hdmi_poll_for_scrambling_enable(const struct
intel_crtc_state *crtc_s
struct drm_connector *_connector);
int intel_hdmi_sink_max_frl_rate(struct drm_connector *connector);
int intel_hdmi_sink_dsc_max_frl_rate(struct drm_connector *connector);
+void intel_hdmi_frl_cfg_write(const struct intel_crtc_state *crtc_state);
/* FRL rate per lane (Gbps) -> PHY PLL table units (10 kbps) */
#define FRL_GBPS_TO_10KBPS(rate) ((rate) * 100000)
--
2.50.1
