The dc8200_pix0 and dc8200_pix1 MUXes feed the display controller, and the rate they carry is ultimately produced by the HDMI PHY, which registers hdmitx0_pixelclk as a clock provider.
Add CLK_SET_RATE_PARENT to both MUXes so a rate requested on them reaches that parent, instead of being clamped to whatever rate the parent already happens to run at. Co-developed-by: Dominique Belhachemi <[email protected]> Signed-off-by: Dominique Belhachemi <[email protected]> Signed-off-by: Michal Wilczynski <[email protected]> --- drivers/clk/starfive/clk-starfive-jh7110-vout.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/starfive/clk-starfive-jh7110-vout.c b/drivers/clk/starfive/clk-starfive-jh7110-vout.c index bad20d5d794a72f071b4d547b7304786a8ba9afa..b608fe358031109a15962a623b1c14d424023c02 100644 --- a/drivers/clk/starfive/clk-starfive-jh7110-vout.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-vout.c @@ -40,10 +40,10 @@ static const struct jh71x0_clk_data jh7110_voutclk_data[] = { JH71X0_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, JH7110_VOUTCLK_VOUT_TOP_AXI), JH71X0_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, JH7110_VOUTCLK_VOUT_TOP_AXI), JH71X0_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, JH7110_VOUTCLK_VOUT_TOP_AHB), - JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2, + JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", CLK_SET_RATE_PARENT, 2, JH7110_VOUTCLK_DC8200_PIX, JH7110_VOUTCLK_HDMITX0_PIXELCLK), - JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2, + JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", CLK_SET_RATE_PARENT, 2, JH7110_VOUTCLK_DC8200_PIX, JH7110_VOUTCLK_HDMITX0_PIXELCLK), /* LCD */ -- 2.34.1
