Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider: - [High] Adding CLK_SET_RATE_PARENT without CLK_SET_RATE_NO_REPARENT on hardware signal-routing muxes allows clk_set_rate() to dynamically hijack the active clock parent. --
commit 09b0c9046fefb467ad795def912713bba900bd11 Author: Michal Wilczynski <[email protected]> clk: starfive: jh7110-vout: Allow pixel clock rate propagation This commit adds CLK_SET_RATE_PARENT to the dc8200_pix0 and dc8200_pix1 MUXes, allowing display controller rate requests to propagate to the parent clock. > diff --git a/drivers/clk/starfive/clk-starfive-jh7110-vout.c > b/drivers/clk/starfive/clk-starfive-jh7110-vout.c > index bad20d5d794a7..b608fe3580311 100644 > --- a/drivers/clk/starfive/clk-starfive-jh7110-vout.c > +++ b/drivers/clk/starfive/clk-starfive-jh7110-vout.c > @@ -40,10 +40,10 @@ static const struct jh71x0_clk_data jh7110_voutclk_data[] > = { > JH71X0_GATE(JH7110_VOUTCLK_DC8200_AXI, "dc8200_axi", 0, > JH7110_VOUTCLK_VOUT_TOP_AXI), > JH71X0_GATE(JH7110_VOUTCLK_DC8200_CORE, "dc8200_core", 0, > JH7110_VOUTCLK_VOUT_TOP_AXI), > JH71X0_GATE(JH7110_VOUTCLK_DC8200_AHB, "dc8200_ahb", 0, > JH7110_VOUTCLK_VOUT_TOP_AHB), > - JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", 0, 2, > + JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX0, "dc8200_pix0", > CLK_SET_RATE_PARENT, 2, > JH7110_VOUTCLK_DC8200_PIX, > JH7110_VOUTCLK_HDMITX0_PIXELCLK), > - JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", 0, 2, > + JH71X0_GMUX(JH7110_VOUTCLK_DC8200_PIX1, "dc8200_pix1", > CLK_SET_RATE_PARENT, 2, > JH7110_VOUTCLK_DC8200_PIX, > JH7110_VOUTCLK_HDMITX0_PIXELCLK), [Severity: High] Does adding CLK_SET_RATE_PARENT without CLK_SET_RATE_NO_REPARENT on these hardware signal-routing muxes allow CCF to unexpectedly reparent the active clock parent? When the display driver calls clk_set_rate() on the dc8200_pix0 or dc8200_pix1 clock, __clk_mux_determine_rate() will evaluate all parents because CLK_SET_RATE_NO_REPARENT is not set. Because the HDMI PHY PLL is highly adjustable, it will likely offer a mathematically closer rate than the generic DC8200_PIX divider. CCF will then select the HDMI PHY as the best parent and dynamically reparent the clock by calling clk_core_reparent(). Could this silently override the display driver's physical routing configuration and sever the physical routing, breaking the display output? -- Sashiko AI review ยท https://sashiko.dev/#/patchset/[email protected]?part=9
