Add device nodes for HDMI (similar to previous one in MSM8998) and HDMI PHY (new Synopsys-based block).
Signed-off-by: Krzysztof Kozlowski <[email protected]> --- arch/arm64/boot/dts/qcom/eliza.dtsi | 94 ++++++++++++++++++++++++++++++++++++- 1 file changed, 92 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi index 66ea4aaafd73..27dd15766f51 100644 --- a/arch/arm64/boot/dts/qcom/eliza.dtsi +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi @@ -2570,7 +2570,14 @@ dpu_intf0_out: endpoint { remote-endpoint = <&mdss_dp0_in>; }; }; - /* TODO: HDMI */ + + port@3 { + reg = <3>; + + dpu_intf4_out: endpoint { + remote-endpoint = <&mdss_hdmi_in>; + }; + }; }; mdp_opp_table: opp-table { @@ -2805,6 +2812,89 @@ mdss_dsi1_phy: phy@ae97000 { status = "disabled"; }; + mdss_hdmi: hdmi@aea0000 { + compatible = "qcom,eliza-hdmi-tx"; + reg = <0x0 0x0aea0000 0x0 0x1000>, + <0x0 0x0aee0000 0x0 0x1000>; + reg-names = "core_physical", + "hdcp_physical"; + + interrupts-extended = <&mdss 8>; + + clocks = <&dispcc DISP_CC_MDSS_HDMI_AHBM_CLK>, + <&dispcc DISP_CC_MDSS_HDMI_APP_CLK>, + <&dispcc DISP_CC_MDSS_HDMI_PCLK_CLK>, + <&dispcc DISP_CC_MDSS_HDMI_INTF_CLK>, + <&mdss_hdmi_phy>, + <&dispcc DISP_CC_MDSS_HDMI_PCLK_CLK_SRC>; + clock-names = "iface", + "core", + "extp", + "phy_iface", + "pll", + "pixel_src"; + + operating-points-v2 = <&mdss_hdmi_opp_table>; + + phys = <&mdss_hdmi_phy>; + power-domains = <&rpmhpd RPMHPD_CX>; + #sound-dai-cells = <1>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_hdmi_in: endpoint { + remote-endpoint = <&dpu_intf4_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_hdmi_out: endpoint { + }; + }; + }; + + mdss_hdmi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + }; + }; + + mdss_hdmi_phy: phy@aea1000 { + compatible = "qcom,eliza-hdmi-phy"; + reg = <0x0 0x0aea1000 0x0 0x1000>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&tcsr TCSR_HDMI_CLKREF_EN>, + <&bi_tcxo_div2>; + clock-names = "iface", + "ref", + "xo"; + + #clock-cells = <0>; + #phy-cells = <0>; + power-domains = <&rpmhpd RPMHPD_CX>; + + status = "disabled"; + }; + mdss_dp0: displayport-controller@af54000 { compatible = "qcom,eliza-dp", "qcom,sm8650-dp"; reg = <0x0 0x0af54000 0x0 0x200>, @@ -2913,7 +3003,7 @@ dispcc: clock-controller@af00000 { <0>, <0>, /* dp3 */ <0>, - <0>; /* HDMI phy */ + <&mdss_hdmi_phy>; /* HDMI phy */ power-domains = <&rpmhpd RPMHPD_MX>; required-opps = <&rpmhpd_opp_low_svs>; -- 2.53.0
