On Fri, Aug 28, 2026 at 03:47:27PM +0200, Michal Wilczynski wrote: > Add the dt-binding for the StarFive JH7110 HDMI subsystem. > > The JH7110 HDMI IP is a monolithic block containing both the digital > controller and analog PHY in a single register space. This binding > defines the parent device, which holds the shared register map and > populates its two children: the PHY and the controller. This is > necessary to resolve a circular clock dependency between the HDMI block > and the VOUT clock generator. > > Signed-off-by: Michal Wilczynski <[email protected]> > --- > .../mfd/starfive,jh7110-hdmi-subsystem.yaml | 116 > +++++++++++++++++++++ > 1 file changed, 116 insertions(+) > > diff --git > a/Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-subsystem.yaml > b/Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-subsystem.yaml > new file mode 100644 > index > 0000000000000000000000000000000000000000..01f079160ab8c13c6fa4ce3abaac6607021b3792 > --- /dev/null > +++ > b/Documentation/devicetree/bindings/mfd/starfive,jh7110-hdmi-subsystem.yaml > @@ -0,0 +1,116 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/mfd/starfive,jh7110-hdmi-subsystem.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: StarFive JH7110 HDMI subsystem > + > +maintainers: > + - Michal Wilczynski <[email protected]> > + > +description: > + The StarFive JH7110 HDMI block is a monolithic IP containing both > + the digital controller logic and the analog PHY logic in a single > + register space. > + > +properties: > + compatible: > + const: starfive,jh7110-hdmi-subsystem > + > + reg: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + description: > + NoC display bus clock, which gates access to the whole vout > + register region. > + > + resets: > + maxItems: 1 > + description: > + NoC display bus reset, which gates access to the whole vout > + register region. > + > + power-domains: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - clocks > + - resets > + - power-domains
Here you're willing not to have -names properties?
> +
> +patternProperties:
> + "^phy(@[0-9a-f]+)?$":
These are not pattern properties at all, given they have no variance
because there's no unit addresses involved!
pw-bot: changes-requested
Cheers,
Conor.
> + $ref: /schemas/phy/starfive,jh7110-inno-hdmi-phy.yaml#
> + "^controller(@[0-9a-f]+)?$":
> + $ref: /schemas/display/bridge/starfive,jh7110-inno-hdmi-controller.yaml#
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/starfive,jh7110-crg.h>
> + #include <dt-bindings/power/starfive,jh7110-pmu.h>
> + #include <dt-bindings/reset/starfive,jh7110-crg.h>
> +
> + soc {
> + #address-cells = <1>;
> + #size-cells = <1>;
> +
> + hdmi@29590000 {
> + compatible = "starfive,jh7110-hdmi-subsystem";
> + reg = <0x29590000 0x4000>;
> + clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_DISP_AXI>;
> + power-domains = <&pwrc JH7110_PD_VOUT>;
> + resets = <&syscrg JH7110_SYSRST_NOC_BUS_DISP_AXI>;
> +
> + controller {
> + compatible = "starfive,jh7110-inno-hdmi-controller";
> + clocks = <&voutcrg JH7110_VOUTCLK_HDMI_TX_SYS>,
> + <&voutcrg JH7110_VOUTCLK_HDMI_TX_MCLK>,
> + <&voutcrg JH7110_VOUTCLK_HDMI_TX_BCLK>,
> + <&hdmi_phy>;
> + clock-names = "sys", "mclk", "bclk", "pclk";
> + interrupts = <99>;
> + phys = <&hdmi_phy>;
> + phy-names = "hdmi-phy";
> + resets = <&voutcrg JH7110_VOUTRST_HDMI_TX_HDMI>;
> + reset-names = "hdmi_tx";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + endpoint {
> + remote-endpoint = <&dpu_out_dpi0>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + endpoint {
> + remote-endpoint = <&hdmi_con_in>;
> + };
> + };
> + };
> + };
> +
> + hdmi_phy: phy {
> + compatible = "starfive,jh7110-inno-hdmi-phy";
> + #clock-cells = <0>;
> + clock-output-names = "hdmi_pclk";
> + clocks = <&xin24m>;
> + clock-names = "refoclk";
> + #phy-cells = <0>;
> + };
> + };
> + };
> +...
>
> --
> 2.34.1
>
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