Am Dienstag, 29. September 2026, 12:31:14 Mitteleuropäische Sommerzeit schrieb Michal Wilczynski: > The Innosilicon HDMI PHY IP is used by several SoCs. They differ in > where the PHY register block sits in the register space and in which > pixel clocks they support, but the pre-PLL programming sequence and the > layout of its registers are the same. > > Add a small library holding that shared part: the pre-PLL configuration > table format, a lookup, clk_ops determine_rate and recalc_rate helpers, > and the pre-PLL register programming. Callers pass a regmap, a register > offset for the PHY block, and their own pixel clock table. > > No driver uses it yet; the users are converted separately. > > Reviewed-by: Chaoyi Chen <[email protected]> > Reviewed-by: Joshua Peisach <[email protected]> > Signed-off-by: Michal Wilczynski <[email protected]>
Reviewed-by: Heiko Stuebner <[email protected]>
