On Wednesday, September 30, 2026 4:05 PM Svyatoslav Ryhel wrote:
> Document 8-bit CPU parallel MIPI DBI Type B interface provided by
> Tegra20/30 SoCs display controller.
>
> Signed-off-by: Svyatoslav Ryhel <[email protected]>
> ---
> .../display/tegra/nvidia,tegra-8bit-cpu.yaml | 138 ++++++++++++++++++
> 1 file changed, 138 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/display/tegra/nvidia,tegra-8bit-cpu.yaml
>
> diff --git
> a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra-8bit-cpu.yaml
> b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra-8bit-cpu.yaml
> new file mode 100644
> index 0000000000000..f0dab608b2936
> --- /dev/null
> +++
> b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra-8bit-cpu.yaml
> @@ -0,0 +1,138 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra-8bit-cpu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Nvidia Tegra DC based MIPI DBI Type B bridge
> +
> +maintainers:
> + - Svyatoslav Ryhel <[email protected]>
> +
> +description: The display controller in Tegra20/30 SoCs features an
> + 8-bit SPI interface that closely resembles the MIPI DBI Type B
> + protocol and is referred to as '8-bit CPU'. Each display controller
> + provides two such interfaces, which can be used to send MIPI DCS
> + commands to initialize and control the panel while image data is
> + transmitted via 16/18/24-line RGB.
> +
> +properties:
> + compatible:
> + const: nvidia,tegra-8bit-cpu
> +
> + dc-gpios:
> + description: Data/command selection pin.
> + maxItems: 1
> +
> + rw-gpios:
> + description: Read/write pin.
> + maxItems: 1
> +
> + cs-gpios:
> + description: Chip select pin.
> + maxItems: 1
> +
> + data-gpios:
> + description: Specifies a set of 8 gpio pins used to transfer data.
> + minItems: 8
> + maxItems: 8
Based on my admittedly brief research, according to the TRM the display
controller can drive all of these pins - of which there are two fixed
sets as you mention - directly. So we'd need to describe which interface
the display is connected to in DT, but not any GPIOs (which they really
aren't).
> +
> + nvidia,init-sequence:
> + $ref: /schemas/types.yaml#/definitions/uint32-array
> + description: Device specific set of values used in DC DISP_SPI_INIT_SEQ
> + registers.
> + minItems: 4
> + maxItems: 4
And AIUI this is panel-specific DBI commands the display controller will
transmit. So ideally the display driver should receive this data from
the panel driver.
Thank you
Mikko
> +
> + panel:
> + type: object
> + description: Node of supported panel driven by the bridge.
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + properties:
> + port@0:
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> + description: Video port for RGB input.
> +
> + properties:
> + endpoint:
> + $ref: /schemas/graph.yaml#/$defs/endpoint-base
> + unevaluatedProperties: false
> +
> + properties:
> + bus-width:
> + enum: [ 16, 18, 24 ]
> +
> + port@1:
> + $ref: /schemas/graph.yaml#/properties/port
> + description: Video port for DBI output (panel or connector).
> +
> + required:
> + - port@0
> + - port@1
> +
> +required:
> + - compatible
> + - ports
> +
> +unevaluatedProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/gpio/gpio.h>
> +
> + dbi-bridge {
> + compatible = "nvidia,tegra-8bit-cpu";
> +
> + dc-gpios = <&gpio 110 GPIO_ACTIVE_HIGH>;
> + rw-gpios = <&gpio 11 GPIO_ACTIVE_HIGH>;
> + cs-gpios = <&gpio 108 GPIO_ACTIVE_HIGH>;
> +
> + data-gpios = <&gpio 32 GPIO_ACTIVE_HIGH>, <&gpio 33
> GPIO_ACTIVE_HIGH>,
> + <&gpio 34 GPIO_ACTIVE_HIGH>, <&gpio 35
> GPIO_ACTIVE_HIGH>,
> + <&gpio 36 GPIO_ACTIVE_HIGH>, <&gpio 37
> GPIO_ACTIVE_HIGH>,
> + <&gpio 38 GPIO_ACTIVE_HIGH>, <&gpio 39
> GPIO_ACTIVE_HIGH>;
> +
> + nvidia,init-sequence = <0x0000002c 0x0 0x0 0x00005000>;
> +
> + panel {
> + compatible = "hit,tx10d07vm0baa";
> +
> + reset-gpios = <&gpio 175 GPIO_ACTIVE_LOW>;
> +
> + avci-supply = <&vcc_2v8_lcd>;
> + iovcc-supply = <&iovcc_1v8_lcd>;
> +
> + backlight = <&backlight>;
> +
> + port {
> + panel_input: endpoint {
> + remote-endpoint = <&bridge_output>;
> + };
> + };
> + };
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> +
> + bridge_input: endpoint {
> + remote-endpoint = <&dpi_output>;
> + };
> + };
> +
> + port@1 {
> + reg = <1>;
> +
> + bridge_output: endpoint {
> + remote-endpoint = <&panel_input>;
> + };
> + };
> + };
> + };
> --
> 2.53.0
>
>
