On Mon, Jul 27, 2026 at 05:33:26PM +0800, Jun Nie wrote:
> To support high-resolution cases that exceed the width constrain
> or scenarios that surpass the maximum MDP clock rate, additional
> pipes are necessary to enable parallel data processing within
> the width constraints and MDP clock rate.
>
> Expand pipe array size to 4. Request 4 mixers and 4 DSCs for
> high-resolution cases where dual interfaces are enabled for virtual
> plane case. More use cases can be incorporated later if quad-pipe
> capabilities are required.
>
> Signed-off-by: Jun Nie <[email protected]>
> Reviewed-by: Dmitry Baryshkov <[email protected]>
> Reviewed-by: Jessica Zhang <[email protected]>
> Patchwork: https://patchwork.freedesktop.org/patch/675418/
> Link:
> https://lore.kernel.org/r/20250918-v6-16-rc2-quad-pipe-upstream-4-v16-10-ff6232e34...@linaro.org
> Signed-off-by: Dmitry Baryshkov <[email protected]>
> ---
> 2 or more SSPPs and dual-DSI interface are need for super wide panel.
> And 4 DSC are preferred for power optimal in this case due to width
> limitation of SSPP and MDP clock rate constrain. This patch set
> extends number of pipes to 4 and revise related mixer blending logic
> to support quad pipe. All these changes depends on the virtual plane
> feature to split a super wide drm plane horizontally into 2 or more sub
> clip. Thus DMA of multiple SSPPs can share the effort of fetching the
> whole drm plane.
>
> The first pipe pair co-work with the first mixer pair to cover the left
> half of screen and 2nd pair of pipes and mixers are for the right half
> of screen. If a plane is only for the right half of screen, only one
> or two of pipes in the 2nd pipe pair are valid, and no SSPP or mixer is
> assinged for invalid pipe.
>
> For those panel that does not require quad-pipe, only 1 or 2 pipes in
> the 1st pipe pair will be used. There is no concept of right half of
> screen.
>
> For legacy non virtual plane mode, the first 1 or 2 pipes are used for
> the single SSPP and its multi-rect mode.
>
> This patch set drop the merged heading 8 patches of v16, only the last
> 2 are revised and split into 4 patches here.
>
> Changes in v21:
> - Add active-CTL constrain to quad-pipe case.
I'm going to post a patch to drop this condition, but anyway.
> - adjust high clock rate constrain to quad-pipe case so that 4K@30Hz
> still use 2 LMs.
Why is it only 4k@30? 4k@60 also can and should use 2LMs.
At this point I'd probably prefer 'use 2LMs unless you have to use
4LMs'.
For example, there is one more fix for dpu_crtc_assign_resources():
int ctl_idx = i * num_ctl / num_lm
> - Link to v20:
> https://lore.kernel.org/all/[email protected]/
>
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> index bd0e720b484fd..d586825015906 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
> @@ -200,7 +200,7 @@ static int dpu_crtc_get_lm_crc(struct drm_crtc *crtc,
> struct dpu_crtc_state *crtc_state)
> {
> struct dpu_crtc_mixer *m;
> - u32 crcs[CRTC_DUAL_MIXERS];
> + u32 crcs[CRTC_QUAD_MIXERS];
>
> int rc = 0;
> int i;
> @@ -1384,6 +1384,9 @@ static struct msm_display_topology
> dpu_crtc_get_topology(
> struct drm_display_mode *mode = &crtc_state->adjusted_mode;
> struct msm_display_topology topology = {0};
> struct drm_encoder *drm_enc;
> + struct msm_drm_private *priv = crtc->dev->dev_private;
> + struct dpu_kms *kms = to_dpu_kms(priv->kms);
There is already a dpu_kms being passed to this function. Please drop.
> + u32 num_rt_intf;
>
> drm_for_each_encoder_mask(drm_enc, crtc->dev, crtc_state->encoder_mask)
> dpu_encoder_update_topology(drm_enc, &topology,
> crtc_state->state,
> @@ -1396,32 +1399,48 @@ static struct msm_display_topology
> dpu_crtc_get_topology(
> *
> * Dual display
> * 2 LM, 2 INTF ( Split display using 2 interfaces)
> + * 4 LM, 2 INTF ( Split display using 2 interfaces and stream merge
> + to support high resolution interfaces if virtual
> + plane is enabled)
> + * If DSC is enabled, use 2:2:2 for 2 LMs case, and 4:4:2 for 4 LMs
> + * case.
> *
> * Single display
> * 1 LM, 1 INTF
> * 2 LM, 1 INTF (stream merge to support high resolution interfaces)
> *
> - * If DSC is enabled, use 2 LMs for 2:2:1 topology
> + * If DSC is enabled, use 2 LMs for 2:2:1 topology for single display
> + * to support legacy devices that use this topology. Use 1:1:1 topology
> + * if there is only one DSC engine in SoC.
> *
> * Add dspps to the reservation requirements if ctm or gamma_lut are
> requested
> - *
> - * Only hardcode num_lm to 2 for cases where num_intf == 2 and CWB is
> not
> - * enabled. This is because in cases where CWB is enabled, num_intf will
> - * count both the WB and real-time phys encoders.
> - *
> - * For non-DSC CWB usecases, have the num_lm be decided by the
> - * (mode->hdisplay > MAX_HDISPLAY_SPLIT) check.
> */
>
> - if (topology.num_intf == 2 && !topology.cwb_enabled)
> - topology.num_lm = 2;
> - else if (topology.num_dsc == 2)
> - topology.num_lm = 2;
> - else if (dpu_kms->catalog->caps->has_3d_merge &&
> - topology.num_dsc == 0)
> - topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
> - else
> - topology.num_lm = 1;
> + num_rt_intf = topology.num_intf;
> + if (topology.cwb_enabled)
> + num_rt_intf--;
> +
> + if ((mode->hdisplay > (dpu_kms->catalog->caps->max_mixer_width *
> num_rt_intf)) ||
> + ((u64)mode->hdisplay * mode->vtotal * drm_mode_vrefresh(mode) >
> + kms->perf.max_core_clk_rate))
> + topology.num_lm = num_rt_intf * 2;
> + else {
> + topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ?
> + 2 : num_rt_intf;
This becomes unreadable. Replace ternary with the if, make it a chain of
if-else.
> + }
> +
> + if (!dpu_use_virtual_planes ||
> + dpu_kms->catalog->mdss_ver->core_major_ver < 5)
> + topology.num_lm = min(2, topology.num_lm);
> +
> + if (!dpu_kms->catalog->caps->has_3d_merge)
> + topology.num_lm = min(num_rt_intf, topology.num_lm);
> +
> + if (topology.num_dsc) {
> + if (num_rt_intf == 1)
> + topology.num_lm = min(2, dpu_kms->catalog->dsc_count);
> + topology.num_dsc = topology.num_lm;
> + }
>
> if (crtc_state->ctm || crtc_state->gamma_lut)
> topology.num_dspp = topology.num_lm;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> index 6eaba5696e8e6..455073c7025b0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h
> @@ -210,7 +210,7 @@ struct dpu_crtc_state {
>
> bool bw_control;
> bool bw_split_vote;
> - struct drm_rect lm_bounds[CRTC_DUAL_MIXERS];
> + struct drm_rect lm_bounds[CRTC_QUAD_MIXERS];
>
> uint64_t input_fence_timeout_ns;
>
> @@ -218,10 +218,10 @@ struct dpu_crtc_state {
>
> /* HW Resources reserved for the crtc */
> u32 num_mixers;
> - struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS];
> + struct dpu_crtc_mixer mixers[CRTC_QUAD_MIXERS];
>
> u32 num_ctls;
> - struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS];
> + struct dpu_hw_ctl *hw_ctls[CRTC_QUAD_MIXERS];
>
> enum dpu_crtc_crc_source crc_source;
> int crc_frame_skip_count;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index eba1d52211f68..058a7c8727f7c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -55,7 +55,7 @@
> #define MAX_PHYS_ENCODERS_PER_VIRTUAL \
> (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES)
>
> -#define MAX_CHANNELS_PER_ENC 2
> +#define MAX_CHANNELS_PER_ENC 4
> #define MAX_CWB_PER_ENC 2
>
> #define IDLE_SHORT_TIMEOUT 1
> @@ -661,7 +661,6 @@ void dpu_encoder_update_topology(struct drm_encoder
> *drm_enc,
> struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
> struct msm_drm_private *priv = dpu_enc->base.dev->dev_private;
Unused (and triggers a warning).
> struct msm_display_info *disp_info = &dpu_enc->disp_info;
> - struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
> struct drm_connector *connector;
> struct drm_connector_state *conn_state;
> struct drm_framebuffer *fb;
> @@ -675,22 +674,12 @@ void dpu_encoder_update_topology(struct drm_encoder
> *drm_enc,
>
> dsc = dpu_encoder_get_dsc_config(drm_enc);
>
> - /* We only support 2 DSC mode (with 2 LM and 1 INTF) */
> - if (dsc) {
> - /*
> - * Use 2 DSC encoders, 2 layer mixers and 1 or 2 interfaces
> - * when Display Stream Compression (DSC) is enabled,
> - * and when enough DSC blocks are available.
> - * This is power-optimal and can drive up to (including) 4k
> - * screens.
> - */
> - WARN(topology->num_intf > 2,
> - "DSC topology cannot support more than 2 interfaces\n");
> - if (topology->num_intf >= 2 || dpu_kms->catalog->dsc_count >= 2)
> - topology->num_dsc = 2;
> - else
> - topology->num_dsc = 1;
> - }
> + /*
> + * Set DSC number as 1 to mark the enabled status, will be adjusted
> + * in dpu_crtc_get_topology()
> + */
> + if (dsc)
> + topology->num_dsc = 1;
>
> connector = drm_atomic_get_new_connector_for_encoder(state, drm_enc);
> if (!connector)
> @@ -2180,8 +2169,8 @@ static void dpu_encoder_helper_reset_mixers(struct
> dpu_encoder_phys *phys_enc)
> {
> int i, num_lm;
> struct dpu_global_state *global_state;
> - struct dpu_hw_blk *hw_lm[2];
> - struct dpu_hw_mixer *hw_mixer[2];
> + struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
> + struct dpu_hw_mixer *hw_mixer[MAX_CHANNELS_PER_ENC];
> struct dpu_hw_ctl *ctl = phys_enc->hw_ctl;
>
> /* reset all mixers for this encoder */
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> index 61b22d9494546..09395d7910ac8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> @@ -302,7 +302,7 @@ static inline enum dpu_3d_blend_mode
> dpu_encoder_helper_get_3d_blend_mode(
>
> /* Use merge_3d unless DSC MERGE topology is used */
> if (phys_enc->split_role == ENC_ROLE_SOLO &&
> - dpu_cstate->num_mixers == CRTC_DUAL_MIXERS &&
> + (dpu_cstate->num_mixers != 1) &&
I think here you should be comparing to 'phys_enc->split_role ==
ENC_ROLE_SOLO ? 1 : 2'. Add separate variable for it.
> !dpu_encoder_use_dsc_merge(phys_enc->parent))
> return BLEND_3D_H_ROW_INT;
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index ba04ac24d5a9e..b1ac84c0b52db 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -24,7 +24,7 @@
> #define DPU_MAX_IMG_WIDTH 0x3fff
> #define DPU_MAX_IMG_HEIGHT 0x3fff
>
> -#define CRTC_DUAL_MIXERS 2
> +#define CRTC_QUAD_MIXERS 4
>
> #define MAX_XIN_COUNT 16
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> index 0e65bf5ddc4a6..fd1f3e7982062 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> @@ -34,7 +34,7 @@
> #define DPU_MAX_PLANES 4
> #endif
>
> -#define STAGES_PER_PLANE 1
> +#define STAGES_PER_PLANE 2
> #define PIPES_PER_STAGE 2
> #define PIPES_PER_PLANE (PIPES_PER_STAGE *
> STAGES_PER_PLANE)
> #ifndef DPU_MAX_DE_CURVES
>
> ---
> base-commit: a913d08e5ea9a491b806e64a24410f6722ddc9b3
> change-id: 20260121-msm-next-quad-pipe-split-ab95b6e3ffd3
>
> Best regards,
> --
> Jun Nie <[email protected]>
>
--
With best wishes
Dmitry
